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HCPL-3180-360

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
13
ThermalModel
(DiscussionappliestoHCPL-3180)
The steady state thermal model for the HCPL-3180 is
shown in Figure 27. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated flows through q
CA
which
raises the case temperature TC accordingly. The value of
q
CA
depends on the conditions of the board design and
is, therefore, determined by the designer. The value of
T
JE
= P
E
* (256°C/W + q
CA
) + P
D
* (57°C/W + q
CA
) + T
A
T
JD
= P
E
* (57°C/W + q
CA
) + P
D
* (111°C/W + q
CA
) + T
A
For example, given P
E
= 45 mW,
P
O
= 250 mW, T
A
= +70 °C and q
CA
= +83 °C/W:
T
JE
= P
E
* 339°C/W + P
D
* 140°C/W + T
A
= 45 mW * 339°C/W + 250 mW * 140°C/W + 70°C
= 120°C
T
JD
= P
E
* 140°C/W + P
D
* 194°C/W + T
A
= 45 mW * 140°C/W + 250 mW * 194°C/W + 70°C
= 125°C
T
JE
and T
JD
should be limited to +125 °C based on the board layout and part
placement (q
CA
) specific to the application.
Figure27.Thermalmodel.
q
CA
= +83 °C/W was obtained from thermal measure-
ments using a 2.5 x 2.5 inch PC board, with small traces
(no ground plane), a single HCPL- 3180 soldered into the
center of the board and still air. The absolute maximum
power dissipation derating specifications assume a q
CA
value of +83 °C/W. From the thermal mode in Figure 27,
the LED and detector IC junction temperatures can be
expressed as:
θ
LD
= 442 °C/W
T
JE
T
JD
θ
LC
= 467 °C/W θ
DC
= 126 °C/W
θ
CA
= 83 °C/W*
T
C
T
A
T
JE
= LED JUNCTION TEMPERATURE
T
JD
= DETECTOR IC JUNCTION TEMPERATURE
T
C
= CASE TEMPERATURE MEASURED AT THE
CENTER OF THE PACKAGE BOTTOM
θ
LC
= LED-TO-CASE THERMAL RESISTANCE
θ
LD
= LED-TO-DETECTOR THERMAL RESISTANCE
θ
DC
= DETECTOR-TO-CASE THERMAL RESISTANCE
θ
CA
= CASE-TO-AMBIENT THERMAL RESISTANCE
*θ
CA
WILL DEPEND ON THE BOARD DESIGN AND
THE PLACEMENT OF THE PART.
T
JE
= P
E
* (q
LC
//q
LD
+ q
DC
) + q
CA
) + P
D
* [
+ q
CA
] + T
A
q
LC
*
q
DC
q
LC
+
q
DC
+ q
LD
T
JD
= P
E
* [
+ q
CA
] + P
D *
(q
LC
//q
LD
+ q
DC
) + q
CA
) + T
A
q
LC
*
q
DC
q
LC
+
q
DC
+ q
LD
14
Figure28.Optocouplerinputtooutputcapacitancemodelfor
unshieldedoptocouplers.
Figure29.Optocouplerinputtooutputcapacitancemodelfor
shieldedoptocouplers.
Figure30.EquivalentcircuitforFigure25duringcommonmodetransient.
CMRwiththeLEDOn(CMR
H
)
A high CMR LED drive circuit must keep the LED on
during common mode transients. This is achieved by
over-driving the LED current beyond the input threshold
so that it is not pulled below the threshold during a
transient. A minimum LED current of 10 mA provides
adequate margin over the maximum I
FLH
of
8 mA to achieve 10 kV/µs CMR.
LEDDriveCircuitConsiderationsforUltraHighCMRPerformance
Without a detector shield, the dominant cause of op-
tocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 28. The HCPL-3180
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the ca-
pacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 29. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or off ) during common mode tran-
sients. For example, the recommended application circuit
(Figure 25), can achieve 10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are dis-
cussed in the next two sections.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
R
g
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5 V
+
–
V
CC
= 20 V
• • •
• • •
0.1
µF
+
–
–
CMRwiththeLEDO(CMR
L
)
A high CMR LED drive circuit must keep the LED off (V
F
≤ V
F(OFF)
) during common mode transients. For example,
during a -dV
CM
/dt transient in Figure 30, the current
flowing through C
LEDP
also flows through the R
SAT
and
V
SAT
of the logic gate. As long as the low state voltage
developed across the logic gate is less than V
F(OFF)
, the
LED will remain off and no common mode failure will
occur.
The open collector drive circuit, shown in Figure 31,
cannot keep the LED off during a +dV
CM
/dt transient,
since all the current flowing through C
LEDN
must be
supplied by the LED, and it is not recommended for ap-
plications requiring ultra high CMR
L
performance. Figure
32 is an alternative drive circuit, which like the recom-
mended application circuit (Figure 25), does achieve
ultra high CMR performance by shunting the LED in the
off state.
Figure31.Notrecommendedopencollectordrivecircuit.
Figure32.RecommendedLEDdrivecircuitforultra-highCMR.
Figure33.Undervoltagelockout.
UnderVoltageLockoutFeature
The HCPL-3180 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the HCPL-3180 supply voltage
(equivalent to the fully charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low
resistance state. When the HCPL-3180 output is in the
high state and the supply voltage drops below the HCPL-
3180 V
UVLO-
threshold (typ 7.5 V) the optocoupler output
will go into the low state. When the HCPL-3180 output is
in the low state and the supply voltage rises above the
HCPL-3180 V
UVLO+
threshold (typ 8.5 V) the optocoupler
output will go into the high state (assume LED is “ON”).
IPMDeadTimeandPropagationDelaySpecications
The HCPL-3180 includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time is
the time during which the high and low side power tran-
sistors are off. Any overlap in Q1 and Q2 conduction will
result in large currents flowing through the power devices
from the high voltage to the low-voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has
just turned off when transistor Q2 turns on, as shown in
Figure 34. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propa-
gation delay difference specification, PDD
MAX
, which is
specified to be 90 ns over the operating temperature
range of -40 °C to +100 °C.
Figure34.MinimumLEDskewforzerodeadtime.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
V
O
– OUTPUT VOLTAGE – V
0
0
(V
CC
- V
EE
) – SUPPLY VOLTAGE – V
10
5
20
14
16
18
10 15
2
20
6
8
4
12
t
PHL MAX
t
PLH MIN
PDD* MAX = (t
PHL
-
t
PLH
)
MAX
= t
PHL MAX
-
t
PLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS, THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

HCPL-3180-360

Mfr. #:
Buy HCPL-3180-360
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 2.0A IGBT Gate Drive
Lifecycle:
New from this manufacturer.
Delivery:
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