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TFF11092HN/N1X

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
TFF11092HN All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 28 March 2013 4 of 17
NXP Semiconductors
TFF11092HN
Low phase noise LO generator for VSAT applications
9. Pinning information
9.1 Pinning
9.2 Pin description
Fig 3. Pin configuration for HVQFN24
001aal726
Transparent top view
V
CC(DIV)
NSL1
NSL2
GND(DIV)
NSL0 n.c.
VTUNE n.c.
CPOUT GND1(BUF)
VREGVCO V
CC(BUF)
LCKDET
GND1(REF)
IN(REF)_P
IN(REF)_N
GND2(REF)
V
CC(REF)
GND3(BUF)
BUF2_P
BUF1_P
BUF2_N
BUF1_N
GND2(BUF)
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
Table 4. Pin description
Symbol Pin Description
VREGVCO 1 Regulated output voltage for VCO loop filter. Connect loop filter to this pin.
CPOUT 2 Charge pump output.
VTUNE 3 Tuning voltage for VCO.
NSL0 4 Divider setting, LSB. Leave open for “1”, connect to GND for “0”. See Table 8
.
NSL1 5 Divider setting. Leave open for “1”, connect to GND for “0”. See Table 8
.
NSL2 6 Divider setting, MSB. Leave open for “1”, connect to GND for “0”. See Table 8
.
LCKDET 7 Lock detect. Lock = 2.5 V; out of lock = 0 V. See Table 6
.
GND1(REF) 8 Ground for REF input. Connect this pin to the exposed diepad landing.
IN(REF)_P 9 Reference signal, non-inverting input. Couple this AC to the source.
IN(REF)_N 10 Reference signal, inverting input. Couple this AC to the source.
GND2(REF) 11 Ground for REF input. Connect this pin to the exposed diepad landing.
V
CC(REF)
12 Supply of the internal regulated voltages. Decouple this pin against
GND2(REF) (pin 11).
V
CC(DIV)
13 Supply of the divider and PFD/CP. Decouple this pin against GND(DIV)
(pin 14).
GND(DIV) 14 Ground of the divider. Connect this pin to the exposed diepad landing.
n.c. 15 not connected
n.c. 16 not connected
GND1(BUF) 17 Ground for RF output. Connect this pin to the exposed diepad landing.
TFF11092HN All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 28 March 2013 5 of 17
NXP Semiconductors
TFF11092HN
Low phase noise LO generator for VSAT applications
10. Functional description
The TFF11092HN consists of the following blocks:
• PLL
• Output buffer
• Lock detector
• Reference input
• Divider settings
The functionality of the blocks will be discussed below.
10.1 PLL
The PLL is formed by the VCO, DIVIDER (possible settings: 16, 32, 64, 128 and 256
(see Table 8
)) and a PFD/CP. The tune voltage is referred to the band gap regulated
voltage: VREGVCO (pin 1).
The loop filter can be set to type 2 or type 3. If a type 2 filter is used, the pins
CPOUT (pin 2) and VTUNE (pin 3) must be interconnected. A 10 pF capacitor is placed
internally between pins CPOUT (pin 2) and VREGVCO (pin 1), and a 30 pF capacitor is
placed between pins VTUNE (pin 3) and VREGVCO (pin 1). See Figure 4
and Figure 5.
Values for the loop filter components are given in Table 5
.
The VCO input voltage range is between 0.1 and 0.9 V
O(reg)VCO
.
V
CC(BUF)
18 Supply voltage for the RF output buffer. Decouple this pin against GND2(BUF)
(pin 19).
GND2(BUF) 19 Ground for RF output. Connect this pin to the exposed diepad landing.
BUF1_N 20 RF output.
BUF2_N 21 RF output.
BUF1_P 22 RF output.
BUF2_P 23 RF output.
GND3(BUF) 24 Ground for RF output. Connect this pin to the exposed diepad landing.
Table 4. Pin description
…continued
Symbol Pin Description
TFF11092HN All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 28 March 2013 6 of 17
NXP Semiconductors
TFF11092HN
Low phase noise LO generator for VSAT applications
10.2 Output buffer
The output consists of a differential pair with 50 collector resistors R
BUF_P
and R
BUF_N
. If
only one output is used, terminate the non used output with the same impedance as the
load (see Figure 8
)
10.3 Lock detector
The lock detector is the output of a window detector. The window detector compares the
output voltage over the charge pump. This voltage is identical to VTUNE when a
type 2 loop filter is used (see Figure 4
). In case of a type 3 loop filter this voltage is filtered
by R2/C3 (see Figure 5
). Due to this filtering the attack and decay time will decrease.
The lower window detector threshold voltage is 7 % of the output voltage on
VREGVCO (pin 1), the upper window detector threshold voltage is 93 % of the output
voltage on VREGVCO (pin 1). The hysteresis is 0.1 V. The output is 2.5 V CMOS
compliant. The values are shown in Table 6
. The timing diagram is shown in Figure 6.
At start-up the LCKDET (pin 7) will be LOW until the circuit has acquired lock.
Fig 4. Type 2 loop filter Fig 5. Type 3 loop filter
001aal727
10 pF
C2
C1
R1
30 pF
3
VTUNE
2
CPOUT
1
VREGVCO
2.7 V
001aal728
10 pF
C2
C3
R2
C1
R1
30 pF
3
VTUNE
2
CPOUT
1
VREGVCO
2.7 V
Table 5. Component values used for characterization
f
i(ref)
Divider value C1 C2 C3 R1 R2
(MHz) (nF) (pF) (pF) () ()
35.273 to 36.016 256 27 82 33 470 560
70.547 to 72.031 128 18 82 33 330 560
141.094 to 144.063 64 18 120 33 270 560
282.188 to 288.125 32 33 270 33 120 560
564.375 to 576.250 16 68 560 33 68 560
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

TFF11092HN/N1X

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Buy TFF11092HN/N1X
Manufacturer:
NXP Semiconductors
Description:
Phase Locked Loops - PLL Low phase noise LO generator forVSAT
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New from this manufacturer.
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