NCD9830
http://onsemi.com
12
Digital Logic
The function of the digital logic is to generate the binary
word to be compared with the input analog signal in each
approximation cycle. The result of each approximation
cycle is stored in the SAR register. In short the digital logic
determines the value of each output bit in a sequential
manner base don the output of the comparator.
ANALOG CHANNELS
The analog inputs (CH0−CH7) are multiplexed into the
on−chip successive approximation, analog−digital
converter. This has a resolution of 8 bits. The basic input
range is 0 V to V
DD
. When not performing a conversion or
being addressed, the ADC core is powered off to preserve
power. The internal clock is also powered off.
REFERENCE
The NCD9830 can operate with either its own internal
2.5 V reference or an externally supplied reference. If using
a 5 V supply then an external 5 V reference needs to be used
in order to provide the full range for the 0 to V
DD
analog
input channels. The internal 2.5 V reference will still be
sufficient to provide full dynamic range for the 0 to V
DD
analog input channels.
SERIAL BUS INTERFACE
Control of the NCD9830 is carried out via the I
2
C bus. The
NCD9830 is connected to this bus as a slave device, under
the control of a master device. The NCD9830 has a 7−bit
serial bus address. The upper 5 bits of the device address are
10010. The lower 2 bits are set by pins 12 and 13. Table 7
shows the 7−bit address for each of the pin states. The
address pins can be connected to V
DD
or GND and the
address is set by the state of these pins on power up.
The logic of this address pin is monitored on power up on
the first I
2
C transaction, more precisely, on the low−to−high
transition at the beginning of the eighth SCL pulse.
The ability to make hardwired changes to the I
2
C slave
address allows the user to avoid conflicts with other devices
sharing the same I
2
C address, for example, if more than one
NCD9830 is used in a system. NCD9830 is compatible to all
three operating modes of I
2
C interface i.e Standard
(100 kHz), Fast (400 kHz) and high speed (3.4 MHz) modes.
Table 7. I
2
C ADDRESS OPTIONS
A1 A0 Address
0 0 0x48
0 1 0x49
1 0 0x4A
1 1 0x4B
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high−to−low
transition on the serial data line SDA while the
serial clock line, SCL, remains high. This indicates
that an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the START condition, and shift in the next eight
bits, consisting of a 7−bit address (MSB first) plus
an R/W bit, which determines the direction of the
data transfer, i.e., whether data will be written to
or read from the slave device. The peripheral
whose address corresponds to the transmitted
address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices
on the bus now remain idle while the selected
device waits for data to be read from or written to
it. If the R/W bit is a 0, the master will write to the
slave device. If the R/W bit is a 1, the master will
read from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, as a low−to−high transition
when the clock is high may be interpreted as a
STOP signal. The number of data bytes that can be
transmitted over the serial bus in a single READ or
WRITE operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In WRITE mode,
the master will pull the data line high during the
10th clock pulse to assert a STOP condition. In
READ mode, the master device will override the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
will then take the data line low during the low
period before the tenth clock pulse, then high
during the tenth clock pulse to assert a STOP
condition.
COMMAND BYTE
NCD9830 can be operated in different modes depending
on the internal power state of different circuit sections and
input configuration (single ended or differential). Command
byte also contains three channel select C
x
bits of the internal
eight channel multiplexer. The format of the command byte
is as follows
The 8 bit command code is used to configure:
• Either a single ended or differential measurement
• Channel to be selected
• Power down/reference options
