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NCD9830DBR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
NCD9830
http://onsemi.com
7
TIMING CHARACTERISTICS
Table 6. I
2
C TIMING
Parameter (Note 3) Symbol Conditions Min Max Unit
Clock Frequency f
SCL
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
10 100
400
3.4
1.7
kHz
kHz
MHz
MHz
Bus Free Time t
BUF
Standard Mode
Fast Mode
4.7
1.3
ms
ms
Start Hold Time (Note 4) t
HD;STA
Standard Mode
Fast Mode
High speed Mode
4.0
600
160
ms
ns
ns
SCL Low Time t
LOW
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
4.7
1.3
160
320
ms
ms
ns
ns
SCL High Time t
HIGH
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
4.0
600
60
120
ms
ns
ns
ns
Start Setup Time t
SU;STA
Standard Mode
Fast Mode
High speed Mode
4.7
600
160
ms
ns
ns
Data Setup Time (Note 5) t
SU;DAT
Standard Mode
Fast Mode
High speed Mode
250
100
10
ns
Data Hold Time (Note 6) t
HD;DAT
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
0
0
0
0
3.45
0.9
70
150
ms
ms
ns
ns
SCL Rise Time t
RCL
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
20+0.1C
B
10
20
1000
300
40
80
ns
ns
ns
ns
SCL Rise Time (after repeated start) t
RCL1
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
20+0.1C
B
10
20
1000
300
80
160
ns
ns
ns
ns
SCL Fall Time t
FCL
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
20+0.1C
B
10
20
300
300
40
80
ns
ns
ns
ns
SDA Rise Time t
RDA
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
20+0.1C
B
10
20
1000
300
80
160
ns
ns
ns
ns
SDA Fall Time t
FDA
Standard Mode
Fast Mode
High speed Mode (100 pF)
High speed Mode (400 pF)
20+0.1C
B
10
20
300
300
80
160
ns
ns
ns
ns
Stop Setup Time t
SU;STO
Standard Mode
Fast Mode
High speed Mode
0.4
600
160
ms
ns
ns
Capacitive load C
B
400 pF
3. Guaranteed by design, but not production tested.
4. Time from 10% of SDA to 90% of SCL.
5. Time for 10%or 90% of SDA to 10% of SCL.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
NCD9830
http://onsemi.com
8
Table 6. I
2
C TIMING
Parameter (Note 3) UnitMaxMinConditionsSymbol
Glitch Immunity t
SP
Fast Mode
High−speed Mode
50
10
ns
ns
Noise margin at high level V
NH
Standard Mode
Fast Mode
High speed Mode
0.2 V
DD
V
Noise margin at low level V
NL
Standard Mode
Fast Mode
High speed Mode
0.1 V
DD
V
3. Guaranteed by design, but not production tested.
4. Time from 10% of SDA to 90% of SCL.
5. Time for 10%or 90% of SDA to 10% of SCL.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
Figure 3. Serial Interface Timing
NCD9830
http://onsemi.com
9
TYPICAL CHARACTERISTICS
T
A
= +25°C, V
DD
= +2.7 V, V
REF
= External 2.5 V, f
SAMPLE
= 50 kHz, unless otherwise stated.
0
FREQUENCY (kHz)
Figure 4. FFT vs. Frequency
0
AMPLITUDE (dB)
0
OUTPUT CODE
Figure 5. INL vs. Code (EXT REF)
0.5
INL (LSB)
25 25050 75 100 125 150 225200175
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
OUTPUT CODE
Figure 6. DNL vs. Code (EXT REF)
0.5
DNL (LSB)
25 25050 75 100 125 150 225200175
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
OUTPUT CODE
Figure 7. INL vs. Code (INT REF)
0.5
INL (LSB)
25 25050 75 100 125 150 225200175
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
OUTPUT CODE
Figure 8. DNL vs. Code (INT REF)
0.5
DNL (LSB)
25 25050 75 100 125 150 225200175
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
−50
TEMPERATURE (°C)
Figure 9. Change in Offset vs. Temperature
0.2
DELTA FROM 25°C (LSB)
−30 130
0.15
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
−10 1109070503010
510152025
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

NCD9830DBR2G

Mfr. #:
Buy NCD9830DBR2G
Manufacturer:
ON Semiconductor
Description:
Analog to Digital Converters - ADC 8-BIT 8-CHANNEL ADC
Lifecycle:
New from this manufacturer.
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