NCD9830DBR2G Datasheet NCD9830DBR2G | P13-P15

NCD9830

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MSB

6 5 4 3 2 1 0

SD C2 C1 C0 PD1 PD0 x x

Bit 7: SD − this configures the type of input to be used. If set

to 0 then the device performs a differential measurement. If

set to 1 then a single ended measurement is made.

Bit 6−4: C2−C0 − these are the channel selection bits. See

Channel Selector table below for more detail.

Bit 3−2: PD1−PD0 − these bits let the use select whether the

ADC is powered on, off and whether the internal reference

is to be used or the external one. See Power Down Selection

Table 8 for more detail.

Table 8. POWER DOWN SELECTION

PD1 PD0 Description

0 0 Power down between ADC conversions

0 1 Internal reference OFF, ADC ON

1 0 Internal reference ON, ADC OFF

1 1 Internal reference ON. ADC ON

Table 9. CHANNEL SELECTOR

CHANNEL SELECTION CONTROL

SD C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0 0 0 0 +IN −IN − − − − − − −

0 0 0 1 − − +IN −IN − − − − −

0 0 1 0 − − − − +IN −IN − − −

0 0 1 1 − − − − − − +IN −IN −

0 1 0 0 −IN +IN − − − − − − −

0 1 0 1 − − −IN +IN − − − − −

0 1 1 0 − − − − −IN +IN − − −

0 1 1 1 − − − − − − −IN +IN −

1 0 0 0 +IN − − − − − − − −IN

1 0 0 1 − − +IN − − − − − −IN

1 0 1 0 − − − − +IN − − − −IN

1 0 1 1 − − − − − − +IN − −IN

1 1 0 0 +IN − − − − − − −IN

1 1 0 1 − − − +IN − − − − −IN

1 1 1 0 − − − − − +IN − − −IN

1 1 1 1 − − − − − − − +IN −IN

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INITIATING CONVERSIONS

Communication in Standard/Fast Mode

Communication in standard/fast mode corresponds to

a clock speed of 100/400 kHz. The device address is sent

over the bus followed by R/W set to 0. This is followed by

the Command byte. If the Command byte is correct the

device initiates the conversion cycle by turning on the

converter circuit after it receives the channel selection bits

(SD, C

-C

) of the Command byte. After receiving the

Command byte the NCD 9830 sends an acknowledge bit.

The device is now ready to be read by the master.

FRAME 2

COMMAND BYTE

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK. BY

NCD9830

SDATA

SCLK

START BY

MASTER

SD C2 C1 C0 PD1 PD0 X X1 0 0 1 0 A1 A0 R/W

ACK. BY

NCD9830

1 19 9

Figure 18. Write Addressing the Device to Write the Command Byte

FRAME 1

SERIAL BUS ADDRESS BYTE

SDATA

SCLK

START/RESTART

MASTER

FRAME 2

FIRST DATA BYTE

D7 D6 D5 D4 D3 D2 D1 D01 0 0 1 0 A1 A0 R/W

1 19 9

ACK. BY

NCD9830

STOP

NOT ACK. BY

MASTER

Figure 19. Conversation between Master and NCD9830 in Standard/Fast Mode

SERIAL BUS ADDRESS BYTE

SDATA

SCLK

START/RESTART

MASTER

HIGH SPEED CLOCK HOLDING LOW

DURING CONVERSION

010 0 1 0

A1 A0

R/W

ACK. BY

NCD9830

D1 D2 D3

D4 D5

CONVERSION TIME

N.ACK. BY

MASTER

STOP. BY

MASTER

CLOCK CONTNUES AFTER

CONVERSION

SDATA

Figure 20. Conversation Between Master and NCD9830 in High Speed Mode

During read operation the device address is sent over the

bus followed by R/W set to 1 followed by the acknowledge

bit from the slave .Data can be read from the device in the

form of a 8 bit byte. The MSB of the data word is D

and

LSB is D

Communication in High Speed Mode

Communication in high speed mode corresponds to

a clock speed of 3.4 MHz. Master initiates a high speed

master code that change the mode from standard/fast to high

speed. The high speed master code format is as follows:

START 0 0 0 0 1 X X X N.ACK

The START condition bit is initiated by master and

N.ACK is initiated by NCD9830. The master code must be

run in fast mode to enter in the high speed mode.

High speed operation does not give enough time span for

a conversion to be completed between the start condition

initiated by the master and the read cycle. Therefore, in high

speed mode NCD9830 stretches the clock at low level after

the read cycle is initiated by the master until the conversion

is complete. Master can decide to remain in high speed mode

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by initiating a RESTART condition instead of STOP at the

end of read sequence. A STOP bit at the end of read cycle

changes the mode back to the standard/fast. A typical high

speed read operation is shown in Figure 20.

Reference Voltage Selection

The internal reference can be turned ON or OFF

depending on the Command byte bit PD

status.

When the device turns on for the first time the internal

reference is OFF. Proper settling time must be allowed while

switching any reference (external or internal) ON or OFF

before any conversion is initiated. Depending on the I

operation mode (standard, fast or high speed) the settling

time would vary.

LAYOUT CONSIDERATIONS

Digital boards are electrically noisy environments, and

the NCD9830 SAR architecture is sensitive to power supply

transients, reference voltage variation and other noise

sources in the circuit. Any sudden transient spike can affect

the accuracy of over all conversion result. So care must be

taken to minimize noise induced at the device inputs. Take

the following precautions:

• Place a 0.1 mF bypass capacitor close to the V

pin. In

extremely noisy environments, where the impedance

between the V

and the power supply is high a bigger

capacitor with capacitance value from 1−10 mF must be

used.

• Extra care must be taken while using external reference

voltage for the device. Using a 5 V external reference

voltage may require to connect the I/O REF pin directly

to V

. Any transient glitches and spikes will induce

a lot of noise in the reference voltage that would

compromise the overall performance of the ADC.

Appropriate measures must be taken to avoid pollution

of reference voltage. Place the component far from the

microprocessor or any other digital circuitry to avoid

high frequency noise injection in the analog portions of

ADC. A clean analog ground must be used with

a dedicated analog ground plane

ORDERING INFORMATION

Device Package Shipping

†

NCD9830DBR2G TSSOP−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

NCD9830DBR2G

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Manufacturer:

ON Semiconductor

Description:

Analog to Digital Converters - ADC 8-BIT 8-CHANNEL ADC

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