MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX111
(V
DD
= 5V ±5%, f
XCLK
= 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, V
REF+
= 1.5V, V
REF-
= 0V, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
LSB
nA500
CONDITIONS
I
IN+
, I
IN-
Input Bias Current
(Note 3) pF10
-0.667 x V
REF
V
IN
0.667 x V
REF
-V
REF
V
IN
V
REF
-0.667 x V
REF
V
IN
0.667 x V
REF
Input Capacitance
-V
REF
V
IN
V
REF
V0V
DD
- 3.2
V
IN+
,
V
IN-
Absolute Input Voltage
Range
V-V
REF
+V
REF
V
IN
Differential Input Voltage
Range
-V
REF
V
IN
V
REF
ppm15V
DD
= 4.75V to 5.25VPower-Supply Rejection
%FSRINL
ppm/°C8
Full-Scale Error
Temperature Drift
Relative Accuracy,
Differential Input
(Notes 3, 5–7)
(Notes 3, 4)
±0.25
±2
%
±0.2
±0.20
DNLDifferential Nonlinearity
(Note 6)
UNITSMIN TYP MAXSYMBOL
ppm/V6
(Note 2)
PARAMETER
14 + POL
+ OFL
RESResolution
CMRR
mV±4Offset Error
Common-Mode Rejection
Ratio
10mV (V
IN+
= V
IN-
) 2.0V
Bits
No-Missing-Codes
Resolution
±0.10
(Note 3)
-8 0
±0.05 ±0.10
Full-Scale Error
Uncalibrated
±0.03 ±0.05
MAX111BM
13 + POL
+ OFL
Bits
±0.18
V
IN+
= V
IN-
= 0V
MAX111BC/E
MAX111AC/E
After gain calibration (Note 5)
V
IN
0.667 x V
REF
0V V
IN
V
REF
V
IN
0.667 x V
REF
0V V
IN
V
REF
0V V
IN
V
REF
V
IN
0.667 x V
REF
%FSRINL
Relative Accuracy,
Single-Ended Input
(IN- = GND)
±0.25
±0.15
±0.10
±0.1
±0.06
MAX111BM
±0.18
MAX111BC/E
MAX111AC/E
ACCURACY (Note 1)
ANALOG INPUTS
-0.667 x V
REF
V
IN
0.667 x V
REF
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS—MAX111 (continued)
(V
DD
= 5V ±5%, f
XCLK
= 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, V
REF+
= 1.5V, V
REF-
= 0V, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
V
V
V4.75 5.25V
DD
Positive Supply Voltage
0.4
ms
V
OL
0.8V
IL
204.80
Output Low Voltage
µA
Input Low Voltage
640 1200
t
CONV
Synchronous Conversion
Time (Note 7)
102,400 clock-cycles/conversion
XCLK, I
SINK
= 200µA
pF10
Reference Input
Capacitance
MHz0.25 1.25
nA
f
OSC
Oversampling Clock
Frequency
(Note 8)
V2.4V
IH
Input High Voltage
(Note 3)
V0 1.5V
REF
960
I
DD
Supply Current V
DD
= 5.25V
Differential Reference
Input Voltage Range
Performance guaranteed by supply rejection test
500
I
REF+
,
I
REF-
Reference Input Current
pF10
V
REF+
= 1.5V, V
REF-
= 0V
0.4
V0V
DD
- 3.2
V
REF+
,
V
REF-
V
DD
- 0.5
V
OH
Output High Voltage
Input Capacitance
Absolute Reference Input
Voltage Range
V
V
DD
- 0.5
f
XCLK
= 500kHz,
continuous-conversion mode
µA±1
XCLK, V
DD
= 4.75V, I
SOURCE
= 200µA
20.48
410
I
DD
I
LKG
Input Leakage Current
XCLK unloaded,
continuous-conversion mode, RC
oscillator operational (Note 9)
(Note 3)
µA±1I
LKG
Leakage Current
pF10Output Capacitance
µA
Digital inputs at 0V or 5V
Power-Down Current
DOUT, BUSY, V
DD
= 4.75V, I
SOURCE
= 1.0mA
V
DD
= 5.25V, V
XCLK
= 0V, PD = 1
V
OUT
= 5V or 0V
(Note 3)
10,240 clock-cycles/conversion
DOUT, BUSY, I
SINK
= 1.6mA
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
CONVERSION TIME
DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = V
DD
)
POWER REQUIREMENTS (all digital inputs at 0V or 5V)
REFERENCE INPUTS
DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V)
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
6 _______________________________________________________________________________________
Note 10: Timing specifications are guaranteed by design. All input control signals are specified with t
r
= t
f
= 5ns
(10% to 90% of +5V) and timed from a +1.6V voltage level.
Note 1: These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection tests. Tests are performed at V
DD
= 5V and V
SS
= -5V (MAX110).
Note 2: 32,768 LSBs cover an input voltage range of ±V
REF
(15 bits). An additional bit (OFL) is set for V
IN
> V
REF
.
Note 3: Guaranteed by design. Not subject to production testing.
Note 4: DNL is less than ±2 counts (LSBs) out of 2
15
counts (±14 bits). The major source of DNL is noise, and this can be further
improved by averaging.
Note 5: See
3-Step Calibration
section in text.
Note 6: V
REF
= (V
REF+
- V
REF-
), V
IN
= (V
IN1+
- V
IN1-
) or (V
IN2+
- V
IN2-
). The voltage is interpreted as negative when the voltage at
the negative input terminal exceeds the voltage at the positive input terminal.
Note 7: Conversion time is set by control bits CONV1–CONV4.
Note 8: Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See
Typical Operating
Characteristics
section for the effect of other clock frequencies. Also read the
Clock Frequency
section.
Note 9: This current depends strongly on C
XCLK
(see
Applications Information
section).
TIMING CHARACTERISTICS (see Figure 6)
(V
DD
= 5V, V
SS
= -5V (MAX110), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
MHz
1.1 3.0MAX11_ BM
RC Oscillator Frequency
1.3 2.8MAX11_ _C/E
2.0T
A
= +25°C
PARAMETER SYMBOL MIN TYP MAX UNITS
80
60
CS to SCLK Hold Time
(Note 10)
t
CSH
0 ns
DIN to SCLK Setup Time
(Note 10)
t
DS
100
ns
DIN to SCLK Hold Time
(Note 10)
t
DH
0 ns
100
60
80
CS to SCLK Setup Time
(Note 10)
t
CSS
100
ns
120
SCLK, XCLK Pulse Width
(Note 10)
t
CK
160
ns
03580
0 100
Data Access Time
(Note 10)
t
DA
0 120
ns
0 60 100
0 120
SCLK to DOUT Valid
Delay (Note 10)
t
DO
0 140
ns
35 80
Bus Relinquish Time
(Note 10)
t
DH
120
ns
MAX11_ BM
MAX11_ _C/E
T
A
= +25°C
MAX11_ BM
MAX11_ _C/E
CONDITIONS
MAX11_ _C/E
MAX11_ _C/E
MAX11_ BM
T
A
= +25°C
MAX11_ BM
T
A
= +25°C
C
LOAD
= 50pF
T
A
= +25°C
C
LOAD
= 50pF
MAX11_ _C/E
T
A
= +25°C
MAX11_ BM
T
A
= +25°C
MAX11_ _C/E/M

MAX110AEWE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 2Ch +/-14Bit Serial
Lifecycle:
New from this manufacturer.
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