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LT3500IMSE#PBF

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LT3500
10
3500fc
OPERATION
The LT3500 is a constant frequency, current mode buck
converter with an internal 2.3A switch plus a linear regula-
tor with 13mA output capability. Control of both outputs
is achieved with a common SHDN pin, internal regulator,
oscillator, undervoltage detect, soft-start, thermal shut-
down and power-on reset.
If the SHDN pin is taken below its 0.8V threshold, the
LT3500 will be placed in a low quiescent current mode.
In this mode the LT3500 typically draws 12µA from the
V
IN
pin.
When the SHDN pin is fl oated or driven above 0.76V, the
internal bias circuits turn on generating an internal regu-
lated voltage, 0.8(V
FB
) and 1V(R
T
/SYNC) references, and
a POR signal which sets the soft-start latch.
As the R
T
/SYNC pin reaches its 1V regulation point, the
internal oscillator will start generating a clock signal at a
frequency determined by the resistor from the R
T
/SYNC
pin to ground. Alternatively, if a synchronization signal is
detected by the LT3500 at the R
T
/SYNC pin, a clock signal
will be generated at the incoming frequency on the rising
edge of the synchronization pulse. In addition, the internal
slope compensation will be automatically adjusted to pre-
vent subharmonic oscillation during synchronization.
The LT3500 is a constant frequency, current mode step-
down converter. Current mode regulators are controlled
by an internal clock and two feedback loops that control
the duty cycle of the power switch. In addition to the
normal error amplifi er, there is a current sense amplifi er
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifi er commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180° shift will occur. The current fed system
will have 90° phase shift at a much lower frequency, but
will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
During power up, the POR signal sets the soft-start latch,
which discharges the SS pin to ensure proper start-up
operation. When the SS pin voltage drops below 100mV,
the V
C
pin is driven low disabling switching and the soft-
start latch is reset. Once the latch is reset the soft-start
capacitor starts to charge with a typical value of 2.75µA.
As the voltage rises above 100mV on the SS pin, the V
C
pin will be driven high by the error amplifi er. When the
voltage on the V
C
pin exceeds 0.8V, the clock set-pulse sets
the driver fl ip-fl op which turns on the internal power NPN
switch. This causes current from V
IN
, through the NPN
switch, inductor and internal sense resistor, to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
V
C
pin, the fl ip-fl op is reset and the internal NPN switch
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceeds the predetermined level at the start of a clock cycle,
the fl ip-fl op will not be set resulting in a further decrease in
inductor current. Since the output current is controlled by
the V
C
voltage, output regulation is achieved by the error
amplifi er continually adjusting the V
C
pin voltage.
The error amplifi er is a transconductance amplifi er that
compares the FB voltage to either the SS pin voltage minus
100mV or an internally regulated 800mV, whichever is
lowest. Compensation of the loop is easily achieved with
a simple capacitor or series resistor/capacitor from the
V
C
pin to ground.
Since the SS pin is driven by a constant current source, a
single capacitor on the soft-start pin will generate controlled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
mum current dictated by the V
C
pin clamp, the SS pin
will be discharged, lowering the regulation point until the
output voltage can be supported by the maximum current.
When overload is removed, the output will soft-start from
the overload regulation point.
LT3500
11
3500fc
V
IN
undervoltage detection or thermal shutdown will
set the soft-start latch, resulting in a complete soft-start
sequence.
The switch driver operates from either the V
IN
or BST volt-
age. An external diode and capacitor are used to generate
a drive voltage higher than V
IN
to saturate the output NPN
and maintain high effi ciency.
In addition to the switching regulator, the LT3500 contains
a NPN linear regulator with a 0.8V reference, and 13mA
current capability. The 0.8 reference will track the SS pin
OPERATION
in the same manner as the switching regulator. The linear
output can also be confi gured to drive an external NPN to
provide a linear regulator with higher current capability.
A power good comparator with 30mV of hysteresis trips
when both FB and LFB are above 90% of the 0.8V refer-
ence. The PG output is an open collector NPN that is off
when the output is in regulation allowing a resistor to pull
the PG pin to a desired voltage. The PG output is an open-
collector NPN that is on when the output is in regulation
providing either drive for an output disconnect transistor
or inverted power good logic.
Choosing the Output Voltage
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
R1= R2
V
OUT1
0.8V
–1
R2 should be 10.0k or less to avoid bias current errors.
Reference designators refer to the Block Diagram in
Figure 1.
Choosing the Switching Frequency
The LT3500 switching frequency is set by resistor R5 in
Figure 1. The R
T
/SYNC pin is internally regulated at 1V.
Setting resistor R5 sets the current in the R
T
/SYNC pin
which determines the oscillator frequency as illustrated
in Figure 2.
The switching frequency is typically set as high as pos-
sible to reduce overall solution size. The LT3500 employs
techniques to enhance dropout at high frequencies but
effi ciency and maximum input voltage decrease due to
switching losses and minimum switch on times. The
maximum recommended frequency can be approximated
by the equation:
Frequency (Hz)=
V
OUT1
+ V
D
V
IN
− V
SW
+ V
D
•
1
t
ON(MIN)
where
V
D
is the forward voltage drop of the catch diode
(D1 Figure 1),
V
SW
is the voltage drop of the internal
switch, and t
ON(MIN)
is the minimum on time of the
switch, all at maximum load current.
Figure 2. Frequency vs R
T
/SYNC Resistance
APPLICATIONS INFORMATION
R
RT/SYNC
(kΩ)
0
FREQUENCY (kHz)
1500
2000
2500
160
3500 F02
1000
500
1250
1750
2250
750
250
0
4020
8060
120 140 180
100
200
LT3500
12
3500fc
APPLICATIONS INFORMATION
Table 1. Effi ciency and Size Comparisons for Different R
RT/SYNC
Values, V
OUT1
= 3.3V
FREQUENCY R
T
/SYNC EFFICIENCY V
IN(MAX)
L C C + L AREA
(mm
2
)
2.5MHz 15k 73.6 12 1µ 10µ 24
2.0MHz 20k 81.5 14 1.5µ 10µ 24
1.5MHz 24.9k 84.5 18 2.2µ 10µ 24
1.0MHz 40.2k 87.3 28 3.3µ 22µ 34
500kHz 90.9k 88.9 36 4.7µ 47µ 40
The following example along with the data in Table 1
illustrates the tradeoffs of switch frequency selection.
Example.
V
IN
= 25V, V
OUT1
= 3.3V, I
OUT1
= 2.0A,
Temperature = 0°C to 85°C
t
ON(MIN)
= 185ns (85°C from Typical Characteris-
tics graph),
V
D
= 0.6V,
V
SW
= 0.4V (85°C)
Max Frequency =
3.3 + 0.6
25 − 0.4 + 0.6
•
1
185ns
~ 835kHz
R
T
/SYNC ~ 49.9k
Frequency ≅ 820kHz
Input Voltage Range
Once the switching frequency has been determined, the
input voltage range of the regulator can be determined.
The minimum input voltage is determined by either the
LT3500’s minimum operating voltage of ~2.8V or by its
maximum duty cycle. The duty cycle is the fraction of time
that the internal switch is on during a clock cycle. The
maximum duty cycle can be determined from the clock
frequency and the minimum off time from the typical
characteristics graph.
This leads to a minimum input voltage of:
V
IN(MIN)
=
V
OUT1
+ V
D
DC
MAX
− V
D
+ V
SW
where V
SW
is the voltage drop of the internal switch,
and
DC
MAX
= 1 – t
OFF(MIN)
• Frequency.
Figure 3 shows a typical graph of minimum input voltage
vs load current for 3.3V and 5V applications.
The maximum input voltage is determined by the absolute
maximum ratings of the V
IN
and BST pins and by the
frequency and minimum duty cycle.
The minimum duty cycle is defi ned as:
DC
MIN
= t
ON(MIN)
• Frequency
Maximum input voltage as:
V
IN(MAX)
=
V
OUT1
+ V
D
DC
MIN
− V
D
+ V
SW
Figure 3. Minimum Input Voltage vs Load Current
LOAD CURRENT (A)
0
INPUT VOLTAGE (V)
3
4
5
1.0 1.6 1.8
3500 F03
2
0.2 0.4 0.6 0.8 1.41.2
6
7
8
2.0
V
OUT1
= 5V START-UP
V
OUT1
= 5V RUNNING
V
OUT1
= 3.3V START-UP
V
OUT1
= 3.3V RUNNING
f
SW
= 1MHz
L = 3.3µH
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LT3500IMSE#PBF

Mfr. #:
Buy LT3500IMSE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Monolithic 2A Step-Down Regulator plus Linear Regulator/Controller
Lifecycle:
New from this manufacturer.
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