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LT3500IMSE#PBF

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LT3500
19
3500fc
Figure 7. Synchronous Signal Powered from Regulator’s Output
LT3500
SYNCHRONIZATION
CIRCUITRY
LDRV
PG
R
T
/SYNC
3500 F07
V
CC
CLK
current proportional to the voltage at the V
C
pin. Note that
the output capacitor integrates this current, and that the
capacitor on the V
C
pin (C
C
) integrates the error amplifi er
output current, resulting in two poles in the loop. In
most cases a zero is required and comes from either the
output capacitor ESR or from a resistor in series with C
C
.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (C
PL
) across the feedback divider may improve
the transient response.
Synchronization
The R
T
/SYNC pin can be used to synchronize the LT3500
to an external clock source. Driving the R
T
/SYNC resistor
with a clock source triggers the synchronization detection
circuitry. Once synchronization is detected, the rising edge
of SW will be synchronized to the rising edge of the R
T
/SYNC
pin signal. An AGC loop will adjust slope compensation
to avoid subharmonic oscillation.
The synchronizing clock signal input to the LT3500 must
have a frequency between 250kHz and 2.5MHz, a duty
cycle between 20% and 80%, a low state below 0.5V and
a high state above 1.6V. Synchronization signals outside
of these parameters will cause erratic switching behavior.
The R
T
/SYNC resistor should be set such that the free
running frequency ((V
RT/SYNC
– V
SYNCLO
)/R
RT/SYNC
) is
approximately equal to the synchronization frequency. If
the synchronization signal is halted, the synchronization
detection circuitry will timeout in typically 10µs at which
time the LT3500 reverts to the free-running frequency based
on the current through R
T
/SYNC. If the R
T
/SYNC pin is held
above 1.1V at any time, switching will be disabled.
If the synchronization signal is not present during regu-
lator start-up (for example, the synchronization circuitry
is powered from the regulator output) the R
T
/SYNC pin
must see an equivalent resistance to ground between 15k
and 200k until the synchronization circuitry is active for
proper start-up operation.
If the synchronization signal powers up in an undetermined
state (V
OL
, V
OH
, Hi-Z), connect the synchronization clock
to the LT3500 as shown in Figure 7. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3500
will start-up with a switching frequency determined by the
resistor from the R
T
/SYNC pin to ground.
APPLICATIONS INFORMATION
If the synchronization signal powers up in a low impedance
state (V
OL
), connect a resistor between the R
T
/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the R
T
/SYNC pin to ground will set the start-up
frequency.
If the synchronization signal powers up in a high impedance
state (Hi-Z), connect a resistor from the R
T
/SYNC pin to
ground. The equivalent resistance seen from the R
T
/SYNC
pin to ground will set the start-up frequency.
LT3500
20
3500fc
If the synchronization signal changes between high and
low impedance states during power up (V
OL
, Hi-Z), connect
the synchronization circuitry to the LT3500 as shown in
the Typical Applications section. This will allow the LT3500
to start up with a switching frequency determined by the
equivalent resistance from the R
T
/SYNC pin to ground.
Shutdown and Undervoltage Lockout
Figure 8 shows how to add an undervoltage lockout (UVLO)
to the LT3500. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
R1=
V
H
− V
L
2μA
R2 =
0.76
V
H
− 0.76
R1
+ 2.5μA
V
H
= Turn-on threshold
V
L
= Turn-off threshold
Example: switching should not start until the input is above
4.75V and is to stop if the input falls below 3.75V.
V
H
= 4.75V
V
L
= 3.75
R1=
4.75 − 3.75
2μA
~ 499k
R2 =
0.76
4.75 − 0.76
499k
+ 2.5μA
~ 71.5k
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to switching nodes is minimized. If high re-
sistor values are used, the SHDN pin should be bypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
Soft-Start
The outputs of the LT3500 regulate to either the SS pin
voltage minus 100mV or an internally regulated 800mV,
whichever is lowest. A capacitor from the SS pin to ground
is charged by an internal 2.75µA current source resulting
in a linear output ramp from 0V to the regulated output
whose duration is given by:
t
RAMP
=
C
SS
• 0.9V
2.75μA
APPLICATIONS INFORMATION
Figure 8. Undervoltage Lockout
+
–
0.76V
2µA
2.5µA
R1
R2C1
SHDN
V
IN
3500 F08
An internal comparator will force the part into shutdown
below the minimum V
IN
of 2.8V. This feature can be
used to prevent excessive discharge of battery-operated
systems.
If an adjustable UVLO threshold is required, the SHDN
pin can be used. The threshold voltage of the SHDN pin
comparator is 0.76V. A 2.5µA internal current source de-
faults the open-pin condition to be operating (see Typical
Performance Characteristics). Current hysteresis is added
LT3500
21
3500fc
APPLICATIONS INFORMATION
The PG pin has a sink capability of 400µA when the FB and
LFB pins are below the threshold and can withstand 40V
when the outputs are in regulation. The PG pin is typically
connected to the output with a resistor and is used as an
error fl ag. The resistor value should be chosen to allow the
PG voltage to drop below 0.4V in an error condition.
Example:
V
OUT1
= 5V, PGSINK
(MIN)
= 200µA
R
PG
= (5 – 0.4)/200µA = 23kΩ
The PG pin has a sink capability of 800µA when the FB
and LFB pins are above the threshold and can withstand
40V when the outputs are not in regulation. The PG pin is
typically used as a drive signal for an output disconnect
device. The PG pull-up resistor should be sized in the
same manner as the PG pull-up resistor.
Linear Regulator
The LT3500 contains an error amplifi er and a NPN output
device which can be confi gured as a linear regulator or as
a linear regulator controller.
With the LFB and LDRV pins confi gured as shown in
Figure 1, the LDRV pin outputs a regulated voltage with a
typical current limit of 13mA.
The LDRV voltage is programmed with a resistor divider
between the output and the LFB pin. Choose the 1% resis-
tors according to:
R3 = R4
V
LDRV
0.8V
–1
R4 should be 10.0k or less to avoid bias current errors.
Reference designators refer to the Block Diagram in
Figure 1.
The reference voltage for the linear regulator (LFB pin)
will track the SS pin in the same manner as the FB pin of
the switching regulator.
At power-up, a reset signal sets the soft-start latch and
discharges the SS pin to approximately 0V to ensure
proper start-up. When the SS pin is fully discharged the
latch is reset and the internal 2.75µA current source starts
to charge the SS pin.
When the SS pin voltage is below 100mV, the V
C
pin is
pulled low which disables switching. As the SS pin voltage
rises above 100mV, the V
C
pin is released and the outputs
are regulated to the SS voltage. When the SS pin voltage
minus 100mV exceeds the internal 0.8V reference, the
outputs are regulated to the reference. The SS pin voltage
will continue to rise until it is clamped at 2V.
In the event of a V
IN
undervoltage lockout, the SHDN pin
driven below 0.8V, or the internal die temperature exceeding
its maximum rating during normal operation, the soft-start
latch is set, triggering a start-up sequence.
In addition, if the load exceeds the maximum output switch
current (switching regulator only), the output will start to
drop causing the V
C
pin clamp to be activated. As long as
the V
C
pin is clamped, the SS pin will be discharged. As
a result, the output will be regulated to the highest volt-
age that the maximum output current can support. For
example, if a 6V output is loaded by 1Ω the SS pin will
drop to 0.5V, regulating the output at 3V (typical current
limit time load, 3A • 1Ω). Once the overload condition is
removed, the output will soft-start from the temporary
voltage level to the normal regulation point.
Since the SS pin is clamped at 2V and has to discharge to
0.9V before taking control of regulation, momentary over-
load conditions will be tolerated without a soft-start recov-
ery. The typical time before the SS pin takes control is:
t
SS(CONTROL)
=
C
SS
• 1.1V
600μA
Power Good Indicators
The PG and PG pins are collector outputs of an internal
comparator. The comparator compares the voltages of
the FB and LFB pins to 90% of the reference voltage with
30mV of hysterisis.
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LT3500IMSE#PBF

Mfr. #:
Buy LT3500IMSE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Monolithic 2A Step-Down Regulator plus Linear Regulator/Controller
Lifecycle:
New from this manufacturer.
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