MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
10 ______________________________________________________________________________________
O
N
M
DH_
DL_
MAX1875A/MAX1876A POWER-ON-OFF SEQUENCING DEFINITIONS
SYMBOL
DEFINITION
SS_
VOUT_
EN
V
L
UVLO
A
B
C
D
E
F
G
HI
J
K
L
Undervoltage lockout trip level is provided in the Electrical Characteristics table.
Internal 5V Linear-Regulator Output
Active-High Enable Input
Output Voltage
Internal Soft-Start Input Signal into Error Amplifier
High-Side Gate-Driver Output
Low-Side Gate-Driver Output
V
L
rising while below the UVLO threshold. EN is low.
V
L
is greater than the UVLO threshold. EN is low.
EN is pulled high.
Normal operation
V
L
enters UVLO.
V
L
exits UVLO.
Resumes normal operation
EN is pulled low.
EN is pulled high.
Resumes normal operation
V
L
drops below UVLO threshold while EN is high.
Resumes normal operation
UVLO is activated and DL_ is latched low.
Exiting UVLO: DL_ remains latched low until the first fall of DH_ is detected.
DL_ is low after EN is pulled low.
UVLO
VL
EN
VOUT_
SS_
DH_
DL_
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
Figure 3. MAX1875A/MAX1876A Detailed Power-On-Off Sequencing
MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
______________________________________________________________________________________ 11
VOUT1
SS1
VOUT2
SS2
DH1
DL1
DH2
DL2
UVLO
A
B
C
D
E
F
G
H
I
J
K
M
L
EN
V
L
P
O
N
MAX1858A POWER-ON-OFF SEQUENCING DEFINITIONS
SYMBOL
DEFINITION
V
L
EN
VOUT1
SS1
VOUT2
SS2
DH1
DL1
DH2
DL2
A
B
Internal 5V Linear-Regulator Output
Active-High Enable Input
Regulator 1 Output Voltage
Regulator 1: Internal Soft-Start Input Signal into Error Amplifier
Regulator 2 Output Voltage
Regulator 2: Internal Soft-Start Input Signal into Error Amplifier
Regulator 1: High-Side Gate-Driver Output
Regulator 1: Low-Side Gate-Driver Output
Regulator 2: High-Side Gate-Driver Output
Regulator 2: Low-Side Gate-Driver Output
V
L
rising while below the UVLO threshold. EN is low.
V
L
is greater than the UVLO threshold. EN is low.
SYMBOL
DEFINITION
D
E
F
Normal operation
V
L
enters UVLO.
V
L
exits UVLO.
UVLO
Undervoltage threshold value is provided in the
Electrical Characteristics table.
EN is pulled high. DH1 and DL1 start switching. DH2 and
DL2 are off.
C
Resumes normal operation. DH1 and DL1 start switching.
DH2 and DL2 are off.
EN is pulled low and then high.
H
G
VOUT1 must reach 0V before restarting due to the cycling
of the enable in region H (above).
VOUT1 recovers.
VOUT2 recovers.
V
L
enters UVLO before VOUT2 fully recovers.
V
L
exits UVLO.
UVLO latches DL_ low.
J
K
L
M
N
O
P
I
Exiting UVLO: DL_ remains latched low until the first fall
of DH_ is detected.
DL_ is high after EN is pulled low and soft-stop is complete.
Figure 4. MAX1858A Detailed Power-On-Off Sequencing
MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
12 ______________________________________________________________________________________
High-Side Gate-Drive Supply (BST_)
Gate-drive voltages for the high-side N-channel switch-
es are generated by the flying-capacitor boost circuits
(Figure 5). A boost capacitor (connected from BST_ to
LX_) provides power to the high-side MOSFET driver.
On startup, the synchronous rectifier (low-side MOSFET)
forces LX_ to ground and charges the boost capacitor to
5V. On the second half-cycle, after the low-side MOSFET
turns off, the high-side MOSFET is turned on by closing
an internal switch between BST_ and DH_. This provides
the necessary gate-to-source voltage to turn on the high-
side switch, an action that boosts the 5V gate-drive
signal above V
IN
. The current required to drive the high-
side MOSFET gates (f
SWITCH
Q
G
) is ultimately drawn
from V
L
.
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving moder-
ate-size N-channel high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen with large V
IN
- V
OUT
differential. The DL_ low-side
drive waveform is always the complement of the DH_
high-side drive waveform (with controlled dead time to
prevent cross-conduction or “shoot-through”). An adap-
tive dead-time circuit monitors the DL_ output and pre-
vents the high-side FET from turning on until DL_ is fully
off. There must be a low-resistance, low-inductance path
from the DL_ driver to the MOSFET gate in order for the
adaptive dead-time circuit to work properly. Otherwise,
the sense circuitry in the MAX1858A/MAX1875A/
MAX1876A interprets the MOSFET gate as “off” while
there is actually charge still left on the gate. Use very
short, wide traces (50mils to 100mils wide if the MOSFET
is 1in from the device). The dead time at the DH-off edge
is determined by a fixed 30ns internal delay.
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch.
Additionally, the MAX1858A/MAX1875A/MAX1876A use
the synchronous rectifier to ensure proper startup of the
boost gate-driver circuit and to provide the current-limit
signal.
The internal pulldown transistor that drives DL_ low is
robust, with a 0.5 (typ) on-resistance. This low on-
resistance helps prevent DL_ from being pulled up dur-
ing the fast rise time of the LX_ node, due to capacitive
coupling from the drain to the gate of the low-side syn-
chronous-rectifier MOSFET. However, for high-current
applications, some combinations of high- and low-side
FETs can cause excessive gate-drain coupling, leading
to poor efficiency, EMI, and shoot-through currents.
This can be remedied by adding a resistor (typically
less than 5) in series with BST_, which increases the
turn-on time of the high-side FET without degrading the
turn-off time (Figure 5).
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a “valley” current-sens-
ing algorithm that uses the on-resistance of the low-side
MOSFET as a current-sensing element. If the current-
sense signal is above the current-limit threshold, the
MAX1858A/MAX1875A/MAX1876A do not initiate a new
cycle (Figure 6). Since valley current sensing is
employed, the actual peak current is greater than the
current-limit threshold by an amount equal to the induc-
tor ripple current. Therefore, the exact current-limit char-
acteristic and maximum load capability are a function of
the low-side MOSFET’s on-resistance, current-limit
threshold, inductor value, and input voltage. The reward
for this uncertainty is robust, lossless overcurrent sens-
ing that does not require costly sense resistors.
V
L
BST_
DH_
LX_
4.7
INPUT
(V
IN
)
MAX1875A
Figure 5. Reducing the Switching-Node Rise Time
INDUCTOR CURRENT
I
LIMIT
I
LOAD
0 TIME
-I
PEAK
Figure 6. “Valley” Current-Limit Threshold Point

MAX1858AEEG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Dual 180 Out Buck Controllers
Lifecycle:
New from this manufacturer.
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