MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
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The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
the Design Procedure section). The current-limit thresh-
old is adjusted with an external resistor at ILIM_ (Figure
1). The adjustment range is from 50mV to 300mV, cor-
responding to resistor values of 100kΩ to 600kΩ. In
adjustable mode, the current-limit threshold across the
low-side MOSFET is precisely 1/10th the voltage seen
at ILIM_. However, the current-limit threshold defaults
to 100mV when ILIM is tied to V
L
. The logic threshold
for switchover to this 100mV default value is approxi-
mately V
L
- 0.5V.
Adjustable foldback current limit reduces power dissi-
pation during short-circuit conditions (see the Design
Procedure section).
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by LX_ and PGND. The IC
must be mounted close to the low-side MOSFET with
short, direct traces making a Kelvin-sense connection
so that trace resistance does not add to the intended
sense resistance of the low-side MOSFET.
Undervoltage Lockout and Startup
IF V
L
drops below 4.2V, the MAX1858A/MAX1875A/
MAX1876A assume that the input supply and reference
voltages are too low to make valid decisions and activate
the undervoltage lockout (UVLO) circuitry, which latches
DL and DH low to inhibit switching. RST is also forced
low during UVLO. To reset the latch and be ready for the
next V
L
rise, V
L
must be pulled below 2.5V.
In addition, to ensure proper startup, the value of the
capacitor at REF to GND must meet the following con-
dition:
C
REF
> ((8.29 x 10
-4
) / V
+_SLOPE
) - (1.97 x 10
-1
/ f
S_MAX
)
where V
+_SLOPE
is the actual input-voltage rise time’s
slew rate.
For example, if the switching frequency is set at
600kHz nominal, which is 660kHz (max), and the input-
voltage rise time’s slew rate is 1.6V/mS, then C
REF
should be greater than 0.22µF. Make sure C
REF
is cho-
sen large enough to cover for worst-case capacitance
tolerances and temperature coefficient.
Enable (EN), Soft-Start, and Soft-Stop
Pull EN high to enable or low to shut down both regula-
tors. See the timing diagrams, Figures 3 and 4, for
more detail.
Output-Voltage Sequencing
After the startup circuitry enables the controller, the
MAX1858A begins the startup sequence. Regulator 1
(OUT1) powers up with soft-start enabled. Once the first
converter’s soft-start sequence ends, regulator 2 (OUT2)
powers up with soft-start enabled. Finally, when both con-
verters complete soft-start and both output voltages
exceed 90% of their nominal values, the reset output
(RST) goes high (see the Reset Output section). Soft-stop
is initiated by pulling EN low. Soft-stop occurs in reverse
order of soft-start, allowing last-on/first-off operation.
Reset Output (
RRSSTT
) (MAX1858A/
MAX1876A Only)
RST is an open-drain output. RST pulls low when either
output falls below 90% of its nominal regulation voltage.
Once both outputs exceed 90% of their nominal regulation
voltages and both soft-start cycles are completed, RST
goes high impedance. To obtain a logic-voltage output,
connect a pullup resistor from RST to the logic supply volt-
age. A 100kΩ resistor works well for most applications. If
unused, leave RST grounded or unconnected.
Clock Synchronization (SYNC, CKO)
SYNC serves two functions: SYNC selects the clock out-
put (CKO) type used to synchronize slave controllers, or it
serves as a clock input so the MAX1858A/MAX1875A/
MAX1876A can be synchronized with an external clock
signal. This allows the MAX1858A/MAX1875A/MAX1876A
to function as either a master or slave. CKO provides a
clock signal synchronized to the MAX1858A/MAX1875A/
MAX1876As’ switching frequency, allowing either in-
phase (SYNC = GND) or 90° out-of-phase (SYNC = V
L
)
synchronization of additional DC-DC controllers (Figure 7).
The MAX1858A/MAX1875A/MAX1876A support the fol-
lowing three operating modes:
• SYNC = GND: The CKO output frequency equals
REG1’s switching frequency (f
CKO
= f
DH1
) and the
CKO signal is in phase with REG1’s switching fre-
quency. This provides 2-phase operation when syn-
chronized with a second slave controller.
• SYNC = V
L
: The CKO output frequency equals two
times REG1’s switching frequency (f
CKO
= 2f
DH1
)
and the CKO signal is phase shifted by 90° with
respect to REG1’s switching frequency. This pro-
vides 4-phase operation when synchronized with a
second MAX1858A/MAX1875A/MAX1876A (slave
controller).
