MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
______________________________________________________________________________________ 19
MOSFET Selection
The MAX1858A/MAX1875A/MAX1876As’ step-down
controller drives two external logic-level N-channel
MOSFETs as the circuit switch elements. The key
selection parameters are:
On-resistance (R
DS(ON)
)
Maximum drain-to-source voltage (V
DS(MAX)
)
Minimum threshold voltage (V
TH(MIN)
)
Total gate charge (Q
g
)
Reverse transfer capacitance (C
RSS
)
Power dissipation
All four N-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at V
GS
4.5V. For maximum efficiency, choose a high-side
MOSFET (N
H
_) that has conduction losses equal to the
switching losses at the optimum input voltage. Check to
ensure that the conduction losses at minimum input
voltage do not exceed MOSFET package thermal limits,
or violate the overall thermal budget. Also, check to
ensure that the conduction losses plus switching losses
at the maximum input voltage do not exceed package
ratings or violate the overall thermal budget.
Ensure that the MAX1858A/MAX1875A/MAX1876A DL_
gate drivers can drive N
L
_. In particular, check that the
dv/dt caused by N
H
_ turning on does not pull up the N
L
_
gate through N
L
_’s drain-to-gate capacitance. This is the
most frequent cause of cross-conduction problems.
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. All MOSFETs must be selected
so that their total gate charge is low enough that V
L
can
power all four drivers without overheating the IC:
MOSFET package power dissipation often becomes a
dominant design factor. I
2
R power losses are the great-
est heat contributor for both high-side and low-side
MOSFETs. I
2
R losses are distributed between N
H
_ and
N
L
_ according to duty factor as shown in the equations
below. Switching losses affect only the high-side
MOSFET, since the low-side MOSFET is a zero-voltage
switched device when used in the buck topology.
Calculate MOSFET temperature rise according to pack-
age thermal-resistance specifications to ensure that
both MOSFETs are within their maximum junction tem-
perature at high ambient temperature. The worst-case
dissipation for the high-side MOSFET (P
NH
) occurs at
both extremes of input voltage, and the worst-case dis-
sipation for the low-side MOSFET (P
NL
) occurs at maxi-
mum input voltage.
I
GATE
is the average DH driver-output current capability
determined by:
where R
DS(ON)DH
is the high-side MOSFET driver’s on-
resistance (5 max), R
GATE
is any series resistance
between DH and BST (Figure 5), and R
GMOSFET
is the
internal gate resistance of the external MOSFET:
where P
NH(CONDUCTION)
is the conduction power loss
in the high-side MOSFET, and P
NL
is the total low-side
power loss.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DL_ and DH_ to increase the MOSFETs’ turn-on
and turn-off times.
PIR
V
V
PP P
PI R
V
V
NH CONDUCTION LOAD DS ON NH
OUT
IN
NH TOTAL NH SWITCHING NH CONDUCTION
NL LOAD DS ON NL
OUT
IN
()()
()( )( )
()
=
=+
=
2
2
1-
I
V
RRR
GATE
L
DS ON DH GATE GMOSFET
=
++
()
2
()
PVIf
QQ
I
NH SWITCHING IN LOAD SW
GS GD
GATE
()
=
+
PVQ f
VL IN G TOTAL SW
×
_
BODE PLOT FOR VOLTAGE-
MODE CONTROLLERS
FREQUENCY (MHz)
GAIN (dB)
0.10.01
-40
-30
-20
-10
0
10
20
30
40
50
0.001 1
f
Z-COMP_A
f
COMP_B
f
LC
f
CO
f
ESR
f
SWITCH
Figure 10. Voltage-Mode Loop Analysis
MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
20 ______________________________________________________________________________________
Applications Information
Dropout Performance
When working with low input voltages, the output-volt-
age adjustable range for continuous-conduction opera-
tion is restricted by the minimum off-time (t
OFF(MIN)
).
For best dropout performance, use the lowest (100kHz)
switching-frequency setting. Manufacturing tolerances
and internal propagation delays introduce an error to
the switching frequency and minimum off-time specifi-
cations. This error is more significant at higher frequen-
cies. Also, keep in mind that transient response
performance of buck regulators operated close to
dropout is poor, and bulk output capacitance must
often be added (see the V
SAG
equation in the Design
Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (I
DOWN
)
as much as it ramps up during the maximum on-time
(I
UP
). The ratio h = I
UP
/I
DOWN
is an indicator of the
ability to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and V
SAG
greatly increases
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows tradeoffs between V
SAG
, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where V
DROP1
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V
DROP2
is
the sum of the resistances in the charging path, includ-
ing high-side switch, inductor, and PC board resis-
tances; and t
OFF(MIN)
is from the Electrical
Characteristics. The absolute minimum input voltage is
calculated with h = 1.
If the calculated V+
(MIN)
is greater than the required
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V
SAG
. If operation near dropout is anticipated,
calculate V
SAG
to be sure of adequate transient
response.
Dropout design example:
V
OUT
= 5V
f
SW
= 600kHz
t
OFF(MIN)
= 250ns
V
DROP1
= V
DROP2
= 100mV
h = 1.5
Calculating again with h = 1 gives the absolute limit of
dropout:
Therefore, V
IN
must be greater than 6V, even with very
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 6.58V.
Improving Noise Immunity
Applications where the MAX1858A/MAX1875A/
MAX1876A must operate in noisy environments can
typically adjust their controller’s compensation to
improve the system’s noise immunity. In particular,
high-frequency noise coupled into the feedback loop
causes jittery duty cycles. One solution is to lower the
crossover frequency (see the Compensation section).
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switch-
ing losses and clean, stable operation. This is especially
true for dual converters where one channel can affect
the other. Refer to the MAX1858 EV kit or MAX1875 EV
kit data sheet for specific layout examples.
If possible, mount all the power components on the top
side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
Isolate the power components on the top side from
the analog components on the bottom side with a
ground shield. Use a separate PGND plane under
the OUT1 and OUT2 sides (referred to as PGND1
and PGND2). Avoid the introduction of AC currents
into the PGND1 and PGND2 ground planes. Run the
power plane ground currents on the top side only.
V
VmV
kHz ns
mV mV V
IN MIN()
()()
=
+
+=
5 100
1 600 250
100 100 6
-
V
VmV
kHz ns
mV mV V
IN MIN()
. ( )( )
.
=
+
+=
5 100
1 1 5 600 250
100 100 6 58
-
V
VV
hf t
VV
IN MIN
OUT DROP
SW OFF MIN
DROP DROP()
()
=
+
+
1
21
1-
-
MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
______________________________________________________________________________________ 21
Use a star-ground connection on the power plane to
minimize the crosstalk between OUT1 and OUT2.
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
Connect GND and PGND together close to the IC.
Do not connect them together anywhere else.
Carefully follow the grounding instructions under
step 4 of the Layout Procedure section.
Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz vs. 1oz) to enhance
full-load efficiency by 1% or more.
LX_ and PGND connections to the synchronous rec-
tifiers for current limiting must be made using Kelvin-
sense connections to guarantee the current-limit
accuracy. With 8-pin SO MOSFETs, this is best done
by routing power to the MOSFETs from outside
using the top copper layer, while connecting PGND
and LX_ underneath the 8-pin SO package.
When trade-offs in trace lengths must be made,
allow the inductor-charging path to be made longer
than the discharge path. Since the average input
current is lower than the average output current in
step-down converters, this minimizes the power dis-
sipation and voltage drops caused by board resis-
tance. For example, allow some extra distance
between the input capacitors and the high-side
MOSFET rather than to allow distance between the
inductor and the low-side MOSFET or between the
inductor and the output filter capacitor.
Ensure that the feedback connection to C
OUT_
is
short and direct.
Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from the sensitive analog areas
(REF, COMP_, ILIM_, and FB_). Use PGND1 and
PGND2 as EMI shields to keep radiated noise away
from the IC, feedback dividers, and analog bypass
capacitors.
Make all pin-strap control input connections (ILIM_,
SYNC, and EN) to analog ground (GND) rather than
power ground (PGND).
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (N
L
_ source, C
IN
_, and C
OUT
_). Make
all these connections on the top layer with wide, cop-
per-filled areas (2oz copper recommended).
2) Mount the controller IC adjacent to the synchronous-
rectifier MOSFETs (N
L
_), preferably on the back
side in order to keep LX_, PGND_, and DL_ traces
short and wide. The DL_ gate trace must be short
and wide, measuring 50mils to 100mils wide if the
low-side MOSFET is 1in from the controller IC.
3) Group the gate-drive components (BST_ diodes and
capacitors, and V
L
bypass capacitor) together near
the controller IC.
4) Make the DC-DC controller ground connections as
follows: create a small analog ground plane near the
IC. Connect this plane to GND and use this plane for
the ground connection for the reference (REF) V+
bypass capacitor, compensation components, feed-
back dividers, OSC resistor, and ILIM_ resistors (if
any). Connect GND and PGND together under the
IC (this is the only connection between GND and
PGND).
5) On the board’s top side (power planes), make a star
ground to minimize crosstalk between the two sides.
Chip Information
TRANSISTOR COUNT: 6688
PROCESS: BiCMOS

MAX1858AEEG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Dual 180 Out Buck Controllers
Lifecycle:
New from this manufacturer.
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