AD7840SQ/883B Datasheet AD7840JPZ, AD7840JNZ, AD7840KPZ | P10-P12

AD7840

REV. B

–9–

Figure 11. AD7840 Dynamic Performance Test Circuit

The digitizer sampling is synchronized with the AD7840 update

rate to ease FFT calculations. The digitizer samples the

AD7840 after the output has settled to its new value. Therefore,

if the digitizer was to sample the output directly it would effec-

tively be sampling a dc value each time. As a result, the dynamic

performance of the AD7840 would not be measured correctly.

Using the digitizer directly on the AD7840 output would give

better results than the actual performance of the AD7840. Us-

ing a filter between the DAC and the digitizer means that the

digitizer samples a continuously moving signal and the true dy-

namic performance of the AD7840 is measured.

Some applications will require improved performance versus fre-

quency from the AD7840. In these applications, a simple

sample-and-hold circuit such as that outlined in Figure 12 will

extend the very good performance of the AD7840 to 20 kHz.

Figure 12. Sample-and-Hold Circuit

Other applications will already have an inherent sample-and-

hold function following the AD7840. An example of this type of

application is driving a switched-capacitor filter where the up-

dating of the DAC is synchronized with the switched-capacitor

filter. This inherent sample-and-hold function also extends the

frequency range performance of the AD7840.

Performance versus Frequency

The typical performance plots of Figures 13 and 14 show the

AD7840’s performance over a wide range of input frequencies

at an update rate of 100 kHz. The plot of Figure 13 is without a

sample-and-hold on the AD7840 output while the plot of Figure

14 is generated with the sample-and-hold circuit of Figure 12 on

the output.

Figure 13. Performance vs. Frequency

(No Sample-and-Hold)

Figure 14. Performance vs. Frequency

(with Sample-and-Hold)

AD7840

REV. B

–10–

MICROPROCESSOR INTERFACING

The AD7840 logic architecture allows two interfacing options

for interfacing the part to microprocessor systems. It offers a

14-bit wide parallel format and a serial format. Fast pulse

widths and data setup times allow the AD7840 to interface

directly to most microprocessors including the DSP processors.

Suitable interfaces to various microprocessors are shown in

Figures 15 to 23.

Parallel Interfacing

Figures 15 to 17 show interfaces to the DSP processors, the

ADSP-2100, the TMS32010 and TMS32020. An external

timer controls the updating of the AD7840. Data is loaded to

the AD7840 input latch using the following instructions:

ADSP-2100: DM(DAC) = MR0

TMS32010: OUT DAC,D

TMS32020: OUT DAC,D

MR0 = ADSP-2100 MR0 Register

D = Data Memory Address

DAC = AD7840 Address

Figure 15. AD7840–ADSP-2100 Parallel Interface

Figure 16. AD7840–TMS32010 Parallel Interface

Figure 17. AD7840–TMS32020 Parallel Interface

Some applications may require that the updating of the AD7840

DAC latch be controlled by the microprocessor rather than the

external timer. One option (for double-buffered interfacing) is

to decode the AD7840

LDAC from the address bus so that a

write operation to the DAC latch (at a separate address than the

input latch) updates the output. An example of this is shown in

the 8086 interface of Figure 18. Note that connecting the

LDAC input to the CS input will not load the DAC latch cor-

rectly since both latches cannot he transparent at the same time.

AD7840–8086 Interface

Figure 18 shows an interface between the AD7840 and the 8086

microprocessor. For this interface, the

LDAC input is derived

from a decoded address. If the least significant address line, A0,

is decoded then the input latch and the DAC latch can reside at

consecutive addresses. A move instruction loads the input latch

while a second move instruction updates the DAC latch and the

AD7840 output. The move instruction to load a data word

WXYZ to the input latch is as follows:

MOV DAC,#YZWX

DAC = AD7840 Address

Figure 18. AD7840–8086 Parallel Interface

AD7840

REV. B

–11–

AD7840–68000 Interface

An interface between the AD7840 and the 68000 microproces-

sor is shown in Figure 19. In this interface example, the

LDAC

input is hardwired low. As a result the DAC latch and analog

output are updated on the rising edge of

WR. A single move

instruction, therefore, loads the input latch and updates the output.

MOVE.W D0,$DAC

D0 = 68000 D0 Register

DAC = AD7840 Address

Figure 19. AD7840–MC68000 Parallel Interface

Serial Interfacing

Figures 20 to 23 show the AD7840 configured for serial inter-

facing with the

CS input hardwired to –5 V. The parallel bus is

not activated during serial communication with the AD7840.

AD7840–ADSP-2101/ADSP-2102 Serial Interface

Figure 20 shows a serial interface between the AD7840 and the

ADSP-2101/ADSP-2102 DSP processor. Also included in the

interface is the AD7870, a 12-bit A/D converter. An interface

such as this is suitable for modem and other applications which

have a DAC and an ADC in serial communication with a

microprocessor.

The interface uses just one of the two serial ports of the

ADSP-2101/ADSP-2102. Conversion is initiated on the

AD7870 at a fixed sample rate (e.g., 9.6 kHz) which is provided

by a timer or clock recovery circuitry. While communication

takes place between the ADC and the ADSP-2101/ ADSP-2102,

the AD7870

SSTRB line is low. This SSTRB line is used to

provide a frame synchronization pulse for the AD7840

SYNC

and ADSP-2101/ADSP-2102 TFS lines. This means that com-

munication between the processor and the AD7840 can only

take place while the AD7870 is communicating with the processor.

This arrangement is desirable in systems such as modems where

the DAC and ADC communication should be synchronous.

The use of the AD7870 SCLK for the AD7840 SCLK and

ADSP-2101/ADSP-2102 SCLK means that only one serial port

of the processor is used. The serial clock for the AD7870 must

be set for continuous clock for correct operation of this interface.

Data from the ADSP-2101/ADSP-2102 is valid on the falling

edge of SCLK. The

LDAC input of the AD7840 is permanently

low so the update of the DAC latch and analog output takes

place on the sixteenth falling edge of SCLK (with

SYNC low).

The FORMAT pin of the AD7840 must be tied to +5 V and

the JUSTIFY pin tied to DGND for this interface to operate

correctly.

Figure 20. Complete DAC/ADC Serial Interface

AD7840–DSP56000 Serial Interface

A serial interface between the AD7840 and the DSP56000 is

shown in Figure 21. The DSP56000 is configured for normal

mode synchronous operation with gated clock. It is also set up

for a 16-bit word with SCK and SC2 as outputs and the FSL

control bit set to a 0. SCK is internally generated on the

DSP56000 and applied to the AD7840 SCLK input. Data from

the DSP56000 is valid on the falling edge of SCK. The SC2

output provides the framing pulse for valid data. This line must

be inverted before being applied to the

SYNC input of the

AD7840.

The

LDAC input of the AD7840 is connected to DGND so the

update of the DAC latch takes place on the sixteenth falling

edge of SCLK. As with the previous interface, the FORMAT

pin of the AD7840 must be tied to +5 V and the JUSTIFY pin

tied to DGND.

Figure 21. AD7840–DSP56000 Serial Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7840SQ/883B

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 14 BIT CMOS IC

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AD7840SQ/883B

AD7840SQ/883B

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