AD7840SQ/883B Datasheet AD7840JPZ, AD7840JNZ, AD7840KPZ | P7-P9

AD7840

REV. B

–6–

OP AMP SECTION

The output from the voltage mode DAC is buffered by a

noninverting amplifier. Internal scaling resistors on the AD7840

configure an output voltage range of ±3 V for an input reference

voltage of +3 V. The arrangement of these resistors around the

output op amp is as shown in Figure 1. The buffer amplifier is

capable of developing ±3 V across a 2 kΩ and 100 pF load to

ground and can produce 6 V peak-to-peak sine wave signals to a

frequency of 20 kHz. The output is updated on the falling edge

of the

LDAC input. The amplifier settles to within 1/2 LSB of

its final value in typically less than 2.5 µs.

The small signal (200 mV p-p) bandwidth of the output buffer

amplifier is typically 1 MHz. The output noise from the ampli-

fier is low with a figure of 30 nV/√

Hz at a frequency of 1 kHz.

The broadband noise from the amplifier exhibits a typical peak-

to-peak figure of 150 µV for a 1 MHz output bandwidth. Figure

4 shows a typical plot of noise spectral density versus frequency

for the output buffer amplifier and for the on-chip reference.

Figure 4. Noise Spectral Density vs. Frequency

TRANSFER FUNCTION

The basic circuit configuration for the AD7840 is shown in Fig-

ure 5. Table II shows the ideal input code to output voltage re-

lationship for this configuration. Input coding to the DAC is 2s

complement with 1 LSB = FS/16,384 = 6 V/16,384 = 366 µV.

Figure 5. AD7840 Basic Connection Diagram

Table II. Ideal Input/Output Code Table

DAC Latch Contents

MSB LSB Analog Output, V

OUT

0 1 1 1 1 1 1 1 1 1 1 1 1 1 +2.999634 V

0 1 1 1 1 1 1 1 1 1 1 1 1 0 +2.999268 V

0 0 0 0 0 0 0 0 0 0 0 0 0 1 +0.000366 V

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V

1 1 1 1 1 1 1 1 1 1 1 1 1 1 –0.000366 V

1 0 0 0 0 0 0 0 0 0 0 0 0 1 –2.999634 V

1 0 0 0 0 0 0 0 0 0 0 0 0 0 –3 V

*Assuming REF IN = +3 V.

The output voltage can be expressed in terms of the input code,

N, using the following expression:

OUT

2× N × REFIN

16384

−8192 ≤ N ≤+8191

INTERFACE LOGIC INFORMATION

The AD7840 contains two 14-bit latches, an input latch and a

DAC latch. Data can be loaded to the input latch in one of two

basic interface formats. The first is a parallel 14-bit wide data

word; the second is a serial interface where 16 bits of data are

serially clocked into the input latch. In the parallel mode,

and

WR control the loading of data. When the serial data format

is selected, data is loaded using the SCLK,

SYNC and SDATA

serial inputs. Data is transferred from the input latch to the

DAC latch under control of the

LDAC signal. Only the data in

the DAC latch determines the analog output of the AD7840.

Parallel Data Format

Table III shows the truth table for AD7840 parallel mode op-

eration. The AD7840 normally operates with a parallel input

data format. In this case, all 14 bits of data (appearing on data

inputs D13 (MSB) through D0 (LSB)) are loaded to the

AD7840 input latch at the same time.

CS and WR control the

loading of this data. These control signals are level-triggered;

therefore, the input latch can be made transparent by holding

both signals at a logic low level. Input data is latched into the in-

put latch on the rising edge of

CS or WR.

The DAC latch is also level triggered. The DAC output is nor-

mally updated on the falling edge of the

LDAC signal. However,

both latches cannot become transparent at the same time.

Therefore, if

LDAC is hardwired low, the part operates as fol-

lows; with

LDAC low and CS and WR high, the DAC latch is

transparent. When

CS and WR go low (with LDAC still low),

the input latch becomes transparent but the DAC latch is dis-

abled. When

CS or WR return high, the input latch is locked

out and the DAC latch becomes transparent again and the DAC

output is updated. The write cycle timing diagram for parallel

data is shown in Figure 6. Figure 7 shows the simplified parallel

input control logic for the AD7840.

AD7840

REV. B

–7–

Table III. Parallel Mode Truth Table

CS WR LDAC Function

HX H

}

Both Latches Latched

XH H

L L H Input Latch Transparent

HH L

}

Input Latch Latched

H X L DAC Latch Transparent

X H L Analog Output Updated

L Input Latch Transparent

DAC Latch Data Transfer Inhibited

}

Input Latch Is Latched

DAC Latch Data Transfer Occurs

X = Don’t Care

Figure 6. Parallel Mode Timing Diagram

Figure 7. AD7840 Simplified Parallel Input Control Logic

Serial Data Format

The serial data format is selected for the AD7840 by connecting

the

CS/SERIAL line to –5 V. In this case, the WR/SYNC,

D13/SDATA, D12/SCLK, D11/FORMAT and D10/JUSTIFY

pins all assume their serial functions. The unused parallel inputs

should not be left unconnected to avoid noise pickup. Serial

data is loaded to the input latch under control of SCLK,

SYNC

and SDATA. The AD7840 expects a 16-bit stream of serial data

on its SDATA input. Serial data must be valid on the falling

edge of SCLK. The

SYNC input provides the frame synchroni-

zation signal which tells the AD7840 that valid serial data will

be available for the next 16 falling edges of SCLK. Figure 8

shows the timing diagram for serial data format.

Figure 8. Serial Mode Timing Diagram

Although 16 bits of data are clocked into the AD7840, only 14

bits go into the input latch. Therefore, two bits in the stream are

don’t cares since their value does not affect the input latch data.

The order and position in which the AD7840 accepts the 14 bits

of input data depends upon the FORMAT and JUSTIFY in-

puts. There are four different input data modes which can be

chosen (see Table I in the Pin Function Description section).

The first mode (M1) assumes that the first two bits of the input

data stream are don’t cares, the third bit is the LSB and the last

(or 16th bit) is the MSB. This mode is chosen by tying both the

FORMAT and JUSTIFY pins to a logic 0. The second mode

(M2; FORMAT = 0, JUSTIFY = 1) assumes that the first bit in

the data stream is the LSB, the fourteenth bit is the MSB and

the last two bits are don’t cares. The third mode (M3;

FORMAT= 1, JUSTIFY 0) assumes that the first two bits in

the stream are again don’t cares, the third bit is now the MSB

and the sixteenth bit is the LSB. The final mode (M4; FOR-

MAT = 1, JUSTIFY= 1) assumes that the first bit is the MSB,

the fourteenth bit is the LSB and the last two bits of the stream

are don’t cares.

AD7840

REV. B

–8–

As in the parallel mode, the LDAC signal controls the loading

of data to the DAC latch. Normally, data is loaded to the DAC

latch on the falling edge of

LDAC. However, if LDAC is held

low, then serial data is loaded to the DAC latch on the sixteenth

falling edge of SCLK. If

LDAC goes low during the transfer of

serial data to the input latch, no DAC latch update takes place

on the falling edge of

LDAC. If LDAC stays low until the serial

transfer is completed, then the update takes place on the six-

teenth falling edge of SCLK. If

LDAC returns high before the

serial data transfer is completed, no DAC latch update takes

place. Figure 9 shows the simplified serial input control logic for

the AD7840.

Figure 9. AD7840 Simplified Serial Input Control Logic

AD7840 DYNAMIC SPECIFICATIONS

The AD7840 is specified and 100% tested for dynamic perfor-

mance specifications as well as traditional dc specifications such

as integral and differential nonlinearity. These ac specifications

are required for the signal processing applications such as

speech synthesis, servo control and high speed modems. These

applications require information on the DAC’s effect on the

spectral content of the signal it is creating. Hence, the param-

eters for which the AD7840 is specified include signal-to-noise

ratio, harmonic distortion and peak harmonics. These terms are

discussed in more detail in the following sections.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal-to-noise ratio at the output of the

DAC. The signal is the rms magnitude of the fundamental.

Noise is the rms sum of all the nonfundamental signals up to

half the sampling frequency (fs/2) excluding dc. SNR is depen-

dent upon the number of quantization levels used in the digiti-

zation process; the more levels, the smaller the quantization

noise. The theoretical signal to noise ratio for a sine wave out-

put is given by

SNR = (6.02N + 1.76) dB (1)

where N is the number of bits. Thus for an ideal 14-bit con-

verter, SNR = 86 dB.

Figure 10 shows a typical 2048 point Fast Fourier Transform

(FFT) plot of the AD7840KN with an output frequency of

1 kHz and an update rate of 100 kHz. The SNR obtained from

this graph is 81.8 dB. It should be noted that the harmonics are

taken into account when calculating the SNR.

Figure 10. AD7840 FFT Plot

Effective Number of Bits

The formula given in (1) relates the SNR to the number of bits.

Rewriting the formula, as in (2) it is possible to get a measure of

performance expressed in effective number of bits (N).

N =

SNR −1. 76

6.02

(2)

The effective number of bits for a device can be calculated

directly from its measured SNR.

Harmonic Distortion

Harmonic distortion is the ratio of the rms sum of harmonics to

the fundamental. For the AD7840, total harmonic distortion

(THD) is defined as

THD = 20log

where V

is the rms amplitude of the fundamental and V

, V

and V

are the rms amplitudes of the second through the

sixth harmonic. The THD is also derived from the 2048-point

FFT plot.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the DAC output

spectrum (up to fs/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification will be

determined by the largest harmonic in the spectrum, but for

parts where the harmonics are buried in the noise floor the peak

will be a noise peak.

Testing the AD7840

A simplified diagram of the method used to test the dynamic

performance specifications is outlined in Figure 11. Data is

loaded to the AD7840 under control of the microcontroller and

associated logic at a 100 kHz update rate. The output of the

AD7840 is applied to a ninth order, 50 kHz, low-pass filter. The

output of the filter is in turn applied to a 16-bit accurate digi-

tizer. This digitizes the signal and the microcontroller generates

an FFT plot from which the dynamic performance of the

AD7840 can be evaluated.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7840SQ/883B

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Digital to Analog Converters - DAC 14 BIT CMOS IC

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AD7840SQ/883B

AD7840SQ/883B

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