AD7840
REV. B
–3–
ORDERING GUIDE
Integral
Temperature SNR Nonlinearity Package
Model
1
Range (dB) (LSB) Option
2
AD7840JN 0°C to +70°C 78 min ±2 max N-24
AD7840KN 0°C to +70°C 80 min ±1 max N-24
AD7840JP 0°C to +70°C 78 min ±2 max P-28A
AD7840KP 0°C to +70°C 80 min ±1 max P-28A
AD7840AQ –25°C to +85°C 78 min ±2 max Q-24
AD7840ARS –25°C to +85°C 78 min ±2 max RS-24
AD7840BQ –25°C to +85°C 80 min ±1 max Q-24
AD7840SQ
3
–55°C to +125°C 78 min ±2 max Q-2
4
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheet and availability.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.
3
This grade will be available to /883B processing only.
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter (J, K, A, B Versions) (S Version) Units Conditions/Comments
t
1
0 0 ns min CS to WR Setup Time
t
2
0 0 ns min CS to WR Hold Time
t
3
45 50 ns min WR Pulse Width
t
4
21 28 ns min Data Valid to WR Setup Time
t
5
10 15 ns min Data Valid to WR Hold Time
t
6
40 40 ns min LDAC Pulse Width
t
7
50 50 ns min SYNC to SCLK Falling Edge
t
8
3
150 200 ns min SCLK Cycle Time
t
9
30 40 ns min Data Valid to SCLK Setup Time
t
10
75 100 ns min Data Valid to SCLK Hold Time
t
11
75 100 ns min SYNC to SCLK Hold Time
NOTES
1
Timing specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 6 and 8.
3
SCLK mark/space ratio is 40/60 to 60/40.
Specifications subject to change without notice.
(V
DD
= +5 V 6 5%, V
SS
= –5 V 6 5%, AGND = DGND = 0 V.)
ABSOLUTE MAXIMUM RATINGS*
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
DD
REF IN to AGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . . –25°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7840 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7840
REV. B
–4–
PIN FUNCTION DESCRIPTION
DIP
Pin Pin
No. Mnemonic Function
1
CS/SERIAL Chip Select/Serial Input. When driven with normal logic levels, it is an active low logic input which is used
in conjunction with
WR to load parallel data to the input latch. For applications where CS is perma-
nently low, an R, C is required for correct power-up (see
LDAC input). If this input is tied to V
SS
, it de-
fines the AD7840 for serial mode operation.
2 WR/SYNC Write/Frame Synchronization Input. In the parallel data mode, it is used in conjunction with CS to load
parallel data. In the serial mode of operation, this pin functions as a Frame Synchronization pulse with se-
rial data expected after the falling edge of this signal.
3 D13/SDATA Data Bit 13(MSB)/Serial Data. When parallel data is selected, this pin is the D13 input. In serial mode,
SDATA is the serial data input which is used in conjunction with
SYNC and SCLK to transfer serial data
to the AD7840 input latch.
4 D12/SCLK Data Bit 12/Serial Clock. When parallel data is selected, this pin is the D12 input. In the serial mode, it is
the serial clock input. Serial data bits are latched on the falling edge of SCLK when
SYNC is low.
5 D11/FORMAT Data Bit 11/Data Format. When parallel data is selected, this pin is the D11 input. In serial mode, a Logic
1 on this input indicates that the MSB is the first valid bit in the serial data stream. A Logic 0 indicates
that the LSB is the first valid bit (see Table I).
6 D10/JUSTIFY Data Bit 10/Data Justification. When parallel data is selected, this pin is the D10 input. In serial mode,
this input controls the serial data justification (see Table I).
7–11 D9–D5 Data Bit 9 to Data Bit 5. Parallel data inputs.
12 DGND Digital Ground. Ground reference for digital circuitry.
13–16 D4–D1 Data Bit 4 to Data Bit 1. Parallel data inputs.
17 D0 Data Bit 0 (LSB). Parallel data input.
18 V
DD
Positive Supply, +5 V ± 5%.
19 AGND Analog Ground. Ground reference for DAC, reference and output buffer amplifier.
20 V
OUT
Analog Output Voltage. This is the buffer amplifier output voltage. Bipolar output range (±3 V with REF
IN = +3 V).
21 V
SS
Negative Supply Voltage, –5 V ± 5%.
22 REF OUT Voltage Reference Output. The internal 3 V analog reference is provided at this pin. To operate the
AD7840 with internal reference, REF OUT should be connected to REF IN. The external load capability
of the reference is 500 µA.
23 REF IN Voltage Reference Input. The reference voltage for the DAC is applied to this pin. It is internally buffered
before being applied to the DAC. The nominal reference voltage for correct operation of the AD7840 is
3 V.
24
LDAC Load DAC. Logic Input. A new word is loaded into the DAC latch from the input latch on the falling
edge of this signal (see Interface Logic Information section). The AD7840 should be powered-up with
LDAC high. For applications where LDAC is permanently low, an R, C is required for correct power-up
(see Figure 19).
Table I. Serial Data Modes
AD7840
REV. B
–5–
PIN CONFIGURATIONS
DIP/SSOP PLCC
for external use, it should he decoupled to AGND with a 200
resistor in series with a parallel combination of a 10 µF tantalum
capacitor and a 0.1 µF ceramic capacitor.
Figure 2. Internal Reference
EXTERNAL REFERENCE
In some applications, the user may require a system reference or
some other external reference to drive the AD7840 reference in-
put. Figure 3 shows how the AD586 5 V reference can be con-
ditioned to provide the 3 V reference required by the AD7840
REF IN. An alternate source of reference voltage for the
AD7840 in systems which use both a DAC and an ADC is to
use the REF OUT voltage of ADCs such as the AD7870 and
AD7871. A circuit showing this arrangement is shown in
Figure 20.
Figure 3. AD586 Driving AD7840 REF IN
D/A SECTION
The AD7840 contains a 14-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The simplified cir-
cuit diagram for the DAC section is shown in Figure 1. The
three MSBs of the data word are decoded to drive the seven
switches A–G. The 11 LSBs switch an 11-bit R-2R ladder struc-
ture. The output voltage from this converter has the same polar-
ity as the reference voltage, REF IN.
The REF IN voltage is internally buffered by a unity gain ampli-
fier before being applied to the D/A converter and the bipolar
bias circuitry. The D/A converter is configured and sealed for a
3 V reference and the device is tested with 3 V applied to REF
IN. Operating the AD7840 at reference voltages outside the
±5% tolerance range may result in degraded performance from
the part.
Figure 1. DAC Ladder Structure
INTERNAL REFERENCE
The AD7840 has an on-chip temperature compensated buried
Zener reference (see Figure 2) which is factory trimmed to 3 V
±10 mV. The reference voltage is provided at the REF OUT
pin. This reference can be used to provide both the reference
voltage for the D/A converter and the bipolar bias circuitry. This
is achieved by connecting the REF OUT pin to the REF IN pin
of the device.
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500 µA to an ex-
ternal load. The maximum recommended capacitance on REF
OUT for normal operation is 50 pF. If the reference is required

AD7840SQ/883B

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 14 BIT CMOS IC
Lifecycle:
New from this manufacturer.
Delivery:
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