ICS844201I-45 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844201BKI-45 REVISION A OCTOBER 7, 2013 4 ©2013 Integrated Device Technology, Inc.
AC Electrical Characteristics
Table 5. AC Characteristics, V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized using a 25MHz crystal.
NOTE 1: Refer to Phase Noise Plots.
NOTE 2: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10
6
clock periods. See IDT Application Note PCI Express Reference Clock Requirements and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for t
REFCLK_HF_RMS
(High Band) and 3.0 ps RMS for t
REFCLK_LF_RMS
(Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency
125 MHz
100 MHz
tjit(Ø)
RMS Phase Jitter,
Random; NOTE 1
125MHz, Integration Range:
12kHz – 20MHz
0.773 ps
100MHz, Integration Range:
12kHz – 20MHz
0.792 ps
t
j
Phase Jitter
Peak-to-Peak;
NOTE 2
125MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
12.51 ps
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
13.48 ps
t
REFCLK_HF_RMS
Phase Jitter RMS;
NOTE 3
125MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.13 ps
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.25 ps
t
REFCLK_LF_RMS
Phase Jitter RMS;
NOTE 3
125MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Low Band: 10kHz - 1.5MHz
0.32 ps
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Low Band: 10kHz - 1.5MHz
0.33 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 450 ps
odc Output Duty Cycle
f
OUT
= 125MHz 48 52 %
f
OUT
= 100MHz 46 54 %
ICS844201I-45 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844201BKI-45 REVISION A OCTOBER 7, 2013 5 ©2013 Integrated Device Technology, Inc.
Typical Phase Noise at 100MHz
Typical Phase Noise at 125MHz
100MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.792ps (typical)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
125MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.773ps (typical)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
ICS844201I-45 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844201BKI-45 REVISION A OCTOBER 7, 2013 6 ©2013 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V LVDS Output Load AC Test Circuit
Output Rise/Fall Time
Offset Voltage Setup
Differential Output Voltage
RMS Phase Jitter
Output Duty Cycle/Pulse Width/Period
Differential Output Voltage Setup
SCOPE
Qx
nQx
3.3V±10%
POWER SUPPLY
+–
Float GND
V
DD
20%
80%
80%
20%
t
R
t
F
V
OD
nQ
Q
V
OD
380mV
(typical)
V
DIFF_OUT
760mV
(typical)
nQ
Q

844201BKI-45LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products FemtoClock Crystal LVDS Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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