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844201BKI-45LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ICS844201I-45 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844201BKI-45 REVISION A OCTOBER 7, 2013 7 ©2013 Integrated Device Technology, Inc.
Application Information
Crystal Input Interface
The ICS844201I-45 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
1 below were determined using a 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
Figure 1. Crystal Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27pF
C2
27pF
ICS844201I-45 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844201BKI-45 REVISION A OCTOBER 7, 2013 8 ©2013 Integrated Device Technology, Inc.
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 2A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 2B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS844201I-45 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844201BKI-45 REVISION A OCTOBER 7, 2013 9 ©2013 Integrated Device Technology, Inc.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (Z
T
) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z
0
) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 3A can be used
with either type of output structure. Figure 3B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS Termination
LVDS
Driver
LVDS
Driver
LVDS
Receiver
LVDS
Receiver
Z
T
C
Z
O
Z
T
Z
O
Z
T
Z
T
2
Z
T
2
Figure 3A. Standard Termination
Figure 3B. Optional Termination
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

844201BKI-45LF

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Manufacturer:
IDT
Description:
Clock Generators & Support Products FemtoClock Crystal LVDS Clock Generator
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New from this manufacturer.
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