13
LTC1142/LTC1142L/LTC1142HV
current. When a load step occurs, V
OUT
shifts by an
amount equal to ∆I
LOAD
• ESR, where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge
or discharge C
OUT
until the regulator loop adapts to the
current change and returns V
OUT
to its steady- state
value. During this recovery time V
OUT
can be monitored
for overshoot or ringing which would indicate a stability
problem. The Pin 27 (13) external components shown in
the Figure 1 circuit will prove adequate compensation for
most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately 25
•
C
LOAD
.
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC1142 circuits:
1. LTC1142 DC bias current
2. MOSFET gate charge current
3. I
2
R losses
1. The DC supply current is the current which flows into
V
IN
(pin 24 for the 3.3V section, Pin 10 for the 5V
section) less the gate charge current. For V
IN
= 10V the
LTC1142 DC supply current for each section is 160µA
with no load, and increases proportionally with load up
to a constant 1.6mA after the LTC1142 has entered
continuous mode. Because the DC bias current is
drawn from V
IN
, the resulting loss increases with input
voltage. For V
IN
= 10V the DC bias losses are generally
less than 1% for load currents over 30mA. However, at
very low load currents the DC bias current accounts for
nearly all of the loss.
2. MOSFET gate charge current results from switching
the gate capacitance of the power MOSFETs. Each time
a MOSFET gate is switched from low to high to low
again, a packet of charge dQ moves from V
IN
to ground.
The resulting dQ/dt is a current out of V
IN
which is
typically much larger than the DC supply current. In
continuous mode, I
GATE(CHG)
= f (Q
N
+ Q
P
). The typical
gate charge for a 0.1Ω N-channel power MOSFET is
25nC, and for a P-channel about twice that value. This
results in I
GATE(CHG)
= 7.5mA in 100kHz continuous
operation, for a 2% to 3% typical mid-current loss with
V
IN
= 10V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it ar-
gues against using larger MOSFETs than necessary to
control I
2
R losses, since overkill can cost efficiency as
well as money!
3. I
2
R losses are easily predicted from the DC resistances
of the MOSFET, inductor, and current shunt. In continu-
ous mode the average output current flows through L
and R
SENSE
, but is “chopped” between the P-channel
and N-channel MOSFETs. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance of
one MOSFET can simply be summed with the resis-
tances of L and R
SENSE
to obtain I
2
R losses. For
example, if each R
DS(ON)
= 0.1Ω, R
L
= 0.15Ω, and
R
SENSE
= 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I
2
R losses cause the
efficiency to roll off at high output currents.
APPLICATIO S I FOR ATIO
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