16
LTC1142/LTC1142L/LTC1142HV
ing with Kelvin connections. Be sure to use a PCB
pattern similar to that shown in Figure 7 for the current
sense resistors.
4. Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? This capaci-
tor provides the AC current to the P-channel MOSFET.
5. Is the input decoupling capacitor (1µF/0.22µF) con-
nected closely between Pin 24 (10) and power ground
[Pin 4 (18) for the LTC1142, Pin 5 (19) for the LTC1142-
ADJ]? This capacitor carries the MOSFET driver peak
currents.
6. Are the shutdown Pins 2 and 16 for the LTC1142 (Pins
3 and 17 for the LTC1142-ADJ) actively pulled to
ground during normal operation? Both Shutdown pins
are high impedance and must not be allowed to float.
Both pins can be driven by the same external signal if
needed.
7. For the LTC1142-ADJ adjustable applications, the re-
sistive divider R1, R2 must be connected between the
(+) plate of C
OUT
and signal ground.
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the C
T
, Pin 25 (11) above
1.5V when the output voltage is greater than the desired
regulated value will turn “on” the N-channel MOSFET for
that regulator section.
A fault condition which causes the output voltage to go
above a maximum allowable value can be detected by
external circuitry. Turning on the N-channel MOSFET
when this fault is detected will cause large currents to flow
and blow the system fuse.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the C
T
pin high and the NDrive Pin 6 (20) going high
is 250ns. Note: Under shutdown conditions, the N-chan-
nel is held OFF and pulling the C
T
pin high will not cause
the N-channel MOSFET to crowbar the output.
A simple N-channel FET can be used as an interface
between the overvoltage detect circuitry and the LTC1142
as shown in Figure 8.
APPLICATIO S I FOR ATIO
WUU
U
Figure 8. Output Crowbar Interface
Figure 9. C
T
Waveforms
Troubleshooting Hints
Since efficiency is critical to LTC1142 applications, it is
very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode
operation.
The waveform to monitor is the voltage on the C
T
, Pins 25
and 11.
In continuous mode (I
LOAD
> I
BURST
) the voltage on the C
T
pin should be a sawtooth with a 0.9V
P-P
swing. This
voltage should never dip below 2V as shown in Figure 9a.
When load currents are low (I
LOAD
< I
BURST
) Burst Mode
operation occurs. The voltage on the C
T
pin now falls to
ground for periods of time as shown in Figure 9b.
Inductor current should also be monitored. Look to verify
that the peak-to-peak ripple current in continuous mode
operation is approximately the same as in Burst Mode
operation.
If Pin 25 or Pin 11 is observed falling to ground at high
output currents, it indicates poor decoupling or improper
grounding. Refer to the Board Layout Checklist.
Auxiliary Windings––Suppressing Burst Mode
Operation
The LTC1142 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary outputs
LTC1142
INT V
CC
C
T
VN2222LL
PIN 26(12)
PIN 25(11)
FROM CROWBAR
DETECT CIRCUIT
(ACTIVE WHEN V
GATE
= V
IN
OFF WHEN V
GATE
= GND)
1142 F08
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode
OPERATION
1142 F09
17
LTC1142/LTC1142L/LTC1142HV
APPLICATIO S I FOR ATIO
WUU
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Figure 10. Suppression of Burst Mode Operation
Figure 11. LTC1142HV-ADJ Dual Regulator with 3.6V/2A and 5V/2A Outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.
Burst Mode
operation can be suppressed at low output
currents with a simple external network which cancels the
25mV minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
certain types of inductors in high current (I
OUT
> 5A)
applications when they are lightly loaded.
An external offset is put in series with the Sense
pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 10. Two 100 resistors are
inserted in series with the sense leads from the sense
resistor.
With the addition of R3 a current is generated through R1
causing an offset of:
VV
R
RR
OFFSET OUT
=•
+
1
13
If V
OFFSET
> 25mV, the built-in offset will be cancelled and
Burst Mode
operation is prevented from occurring. Since
V
OFFSET
is constant, the maximum load current is also
decreased by the same offset. Thus, to get back to the
same I
MAX
, the value of the sense resistor must be lower:
R
mV
I
SENSE
MAX
75
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 1 (15) and Pins 28 (14).
R
SENSE
1000pF
R2
100
R1
100
R3
+
C
OUT
V
OUT
SENSE
+
[PIN 1(15)]
SENSE
[PIN 28(14)]
1142 F10
TYPICAL APPLICATIO S
U
1000pF
+
+
+
1000pF
PDRIVE 1
SENSE
+
1
SENSE
1
NDRIVE 1
PGND1 SGND1 C
T1
I
TH1
I
TH2
C
T2
SGND2
PGND2
NDRIVE 2
SENSE
2
V
FB2
V
FB1
SENSE
+
2
PDRIVE 2
V
IN1
SHDN1
SHDN2
V
IN2
LTC1142HV-ADJ
C
T2
270pF
5 4 25 27 13 11 18 19
R
C2
1k
C
C1
3300pF
C
C2
3300pF
C
T1
270pF
R
C1
1k
0.22µF
3
24 17
100pF
100pF
10
9
15
14
16
20
23
1
28
2
6
V
OUT2
5V/2A
C
OUT2
220µF
10V
× 2
R
SENSE2
0.05
P-CH
Si9430DY
L2
33µH
D2
MBRS130T3
N-CH
Si9410DY
0V = NORMAL
>1.5V = SHDN
0.22µF
C
IN2
22µF
35V
× 2
C
IN1
22µF
35V
× 2
P-CH
Si9430DY
N-CH
Si9410DY
D1
MBRS130T3
C
OUT1
220µF
10V
× 2
L1
27µH
R
SENSE1
0.05
R2
100k
1%
R4
150k
1%
R3
49.9k
1%
R1
52.3k
1%
V
OUT1
3.6V/2A
V
IN
5.2V TO 18V
R
SENSE1,
R
SENSE2
: DALE WSL-2010-.05
L1: SUMIDA CDRH125-270
L2: SUMIDA CDRH125-330
1142 F11
+
(For additional high efficiency circuits, see Application Note 54)
18
LTC1142/LTC1142L/LTC1142HV
Figure 12. LTC1142HV-ADJ High Efficiency Regulator with 3.3V/2A and 2.5V/1.5A Outputs
Figure 13. LTC1142HV High Efficiency Regulator with 3.3V/3A and 5V/2A Outputs
1000pF
+
+
+
1000pF
PDRIVE 1
SENSE
+
1
SENSE
1
NDRIVE 1
PGND1 SGND1 C
T1
I
TH1
I
TH2
C
T2
SGND2
PGND2
NDRIVE 2
SENSE
2
V
FB2
V
FB1
SENSE
+
2
PDRIVE 2
V
IN1
SHDN1
SHDN2
V
IN2
LTC1142HV-ADJ
C
T2
330pF
5 4 25 27 13 11 18 19
R
C2
1k
C
C1
3300pF
C
C2
3300pF
C
T1
330pF
R
C1
1k
0.22µF
3
24 17
100pF
100pF
10
9
15
14
16
20
23
1
28
2
6
V
OUT2
3.3V/2A
C
OUT2
220µF
10V
× 2
R
SENSE2
0.05
P-CH
Si9430DY
L2
25µH
D2
MBRS130T3
N-CH
Si9410DY
0V = NORMAL
>1.5V = SHDN
0.22µF
C
IN2
22µF
35V
× 2
C
IN1
22µF
35V
× 2
P-CH
Si9430DY
N-CH
Si9410DY
D1
MBRS130T3
C
OUT1
220µF
10V
× 2
L1
33µH
R
SENSE1
0.075
R2
49.9k
1%
R4
84.5k
1%
R3
51k
1%
R1
49.9k
1%
V
OUT1
2.5V/1.5A
V
IN
4.5V TO 18V
R
SENSE1
: IRC L1206-01-R075-J
R
SENSE2
: IRC L1206-01-R050-J
1142 F12
+
L1: COILTRONICS CTX33-4
L2: COILTRONICS CTX25-4
+
+
+
1000pF
PDRIVE 3
SENSE
+
3
SENSE
3
NDRIVE 3
PGND3 SGND3 C
T3
I
TH3
I
TH5
C
T5
SGND5
PGND5
NDRIVE 5
SENSE
5
SENSE
+
5
PDRIVE 5
V
IN3
SHDN3
SHDN5
V
IN5
LTC1142HV
C
T5
150pF
4 3 25 27 13 11 17 18
R
C5
1k
C
C3
3300pF
C
C5
3300pF
C
T3
200pF
R
C3
510
0.22µF
2
24 16 10
9
15
14
20
23
1
28
6
V
OUT5
5V/2A
C
OUT5
220µF
10V
× 2
R
SENSE5
0.05
L2
22µH
D2
MBRS130T3
N-CH
Si9410DY
0V = NORMAL
>1.5V = SHDN
0.22µF
C
IN5
22µF
25V
× 2
C
IN3
22µF
25V
× 2
P-CH
Si9433DY
N-CH
Si9410DY
D1
MBRS130T3
C
OUT3
100µF
10V
× 3
L1
10µH
R
SENSE3
0.033
V
OUT3
3.3V/3A
V
IN
5.2V TO 18V
1142 F13
+
P-CH
Si9430DY
1000pF
R
SENSE3
: IRC L1206-01-R033-J
R
SENSE5
: IRC L1206-01-R050-J
L1: COILCRAFT D03316P-103
L2: COILCRAFT D03316P-223
TYPICAL APPLICATIO S
U

LTC1142HVCG-ADJ#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Adj HV Dual Hi Eff Sw Reg Control
Lifecycle:
New from this manufacturer.
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