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LC72717PW-H

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
LC72717PW
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22
(2) Error-corrected Data Output Timing (Basic Restrictions)
Data received by LSI is corrected error and written sequentially without any interruption into the output data buffer
memory. Since this data buffer memory has a capacity for one-block data, the corrected data before reading is over-
written by the next data if data read is delayed. In consequence, it is essential to read data according to the timing
stipulations shown below.
This LSI specifies the output timing for each of horizontally and vertically corrected data as follows:
Upon completion of preparation for the output data, LSI lowers the INT pin to “L” as a request for transmission.
Data output has the period during which only horizontal data can be read and the period during which horizontal and
vertical data are read according to the time division.
Complete data transmission within about 8ms after INT = “L”. When only the horizontally-corrected data can be
output, data transmission is possible for about 17ms. Even when CPU is in the course of reading, the output buffer is
overwritten by the next output data once the specified time period is expired.
The data amount that can be read by one horizontal and vertical transmission request (INT) is one block only.
Vertically-corrected data is output sequentially beginning with the first block after completion of vertical correction,
but the data of parity block is not output.
Horizontal data output period
Horizontal data output
period
Vertical data output
period
Period during which data guarantee is impossible
Output of only horizontal data
Divided output for horizontal and
vertical data
1ms
18ms
990s 990s
INT
1ms
9ms
INT
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(3) Horizontally-corrected Data Output Timing (Relationship With The Received Data)
The timing relationship between the received data and interrupt control signal (INT) for horizontary-corrected data
output is shown. But the delay from the actual received signal caused by demodulation in the MSK demodulation block
is ignored.
Block synchronization is established by determining the BIC code. Data of the Nth packet can be output during
receiving of the next (N + 1) packet data.
(4) Vertically-corrected Data Output Timing
Vertical correction is made when the data of one frame is stored in the memory, frame synchronization has been
established, and when horizontal correction cannot correct all of packet data. Vertical correction start timing is the head
of a frame. During receiving of the first to 28
th
packets of the N-th frame, horizontal correction of each packet is made,
transferring data to the CPU interface. Using the idling time in this period, vertical correction of the previous (N-1)-th
frame data is made.
Vertically-corrected data is output for the amount equivalent to 190 blocks sequentially beginning with reception of the
29
th
packet (block), in such a manner that one block data is output each time one block is received. Only data of data
block in the FM multiplex broadcasting frame is output.
The final 190
th
block is output during reception of the 218
th
block.
In the vertically-corrected data output timing, the packet data corrected by vertical correction is not output (INT not
issued). However, vertical correction data output order is not shortened for the amount equivalent to the packet data that
is not output. For example, if the first to 100
th
data packets have been horizontally corrected, the 101
st
vertically
corrected packet data is output, not at the reception point of the block Number 29
th
, but at the 129
th
packet data
reception point.
(N-1) packet
N packet
(N+1) packet
Received data
(N-1) packet data output period
Period during which data cannot be guaranteed
N packet data output period
BIC BIC
18ms
300ns max
62.5s
300ns max
1ms
BCK
INT
990s
Data output period after
vertical correction of
previous frame
Reception block No.
N-th frame
(N-1)-th frame
271 272 1 2 3 28 29 30 31 218 219 220
18ms
1ms
1 2 189 190
BCK
FCK
INT
18ms
9ms
9ms
18ms28=504ms
62.5s
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(5) List of Operation Modes
Depending on the set value of INT_MOVE (bit 5 of control register 1) and VEC_OUT (bit 2 of control register 2), the
INT signal output timing and output data are modified. In the table below, indicates “output”, indicates “no
output.” and - indicates “none applicable.”
Parameter INT_MOVE VEC_OUT
Horizontal
correction
result
Horizontally-corrected output
Vertically-corrected
output
OK data NG data Parity OK data NG data
Default value 0 0
OK - -
NG *1
Mode 1 1 1
OK - *2 -
NG *2
Mode 2 1 0
OK - *3 -
NG *4
Mode 3 0 1
OK - -
NG
*1 Only data whose horizontal correction result is NG and whose vertical correction result is OK is output.
*2 All of vertically-corrected outputs (190 blocks/frame) are output, in both cases of horizontal correction result of OK
and NG, regardless of whether the vertical correction result is OK or NG.
*3 The vertically-corrected data is not output when there is no data that is determined to be NG because all the
horizontal correction results are OK.
*4 When there is any data whose horizontal correction result becomes NG, all of vertically-corrected outputs
(190 blocks/frame) are output regardless of whether the vertical correction result is OK or NG.
(6) Output Format with DO_MOVE=1
The relationship between INT and DO is shown below. DO becomes “L” in synchronous with the falling edge of INT,
and return to “H” before 3ms or more against the next falling edge of INT. Therefore, when the data read is started
while DO is “L”, there is margin time 3ms or more against the falling edge of INT. This timing diagram is for the
case when the data read is not performed. When the data read is performed, DO returns to “H” after completion of
read.
DO
(Output of only horizontal data)
18ms
Horizontal data output period
990s
Period during which data cannot be guaranteed
1ms
INT
3ms or
more
9ms
990s
DO
(Output of horizontal and
vertical data)
1ms
INT
990s
Horizontal data output
period
Period during which data cannot be guaranteed
Vertical data output
period
3ms or
more
3ms or
more
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LC72717PW-H

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Manufacturer:
ON Semiconductor
Description:
RF Receiver DARC DECODE-LSI
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