OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LC72717PW-H

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
LC72717PW
www.onsemi.com
7
Continued from preceding page.
Pin No. Name of Pin IO Form State with RST=”L”
Description of Functions
17 D0 I/O Input
Data bus 0 to 7 I/O pins (parallel IF)
Bus width switched to 8 bits or 16 bits according to the BUSWD setting
* Connect to Vssd when CCB IF (SP=H) is to be used.
18 D1 I/O Input
19 D2 I/O Input
20 D3 I/O Input
21 D4 I/O Input
22 D5 I/O Input
23 D6 I/O Input
24 D7 I/O Input
25 D8 O Hi-Z
Data bus 8 to 15 output pins (parallel IF)
* Output OFF for 8 bit bus width (BUSWD=L)
26 D9 O Hi-Z
27 D10 O Hi-Z
28 D11 O Hi-Z
29 D12 O Hi-Z
30 D13 O Hi-Z
31 D14 O Hi-Z
32 D15 O Hi-Z
33 INT O H
Interrupt output pin for external CPU
34 Vddd - -
Digital power pin
35 Vssd - -
Digital GND pin
36 OD O Hi-Z(H)
OD output pin (CCB IF)
37 NC - -
NC pin (This pin must be open.)
38 WR I Input
Write control signal input pin (parallel IF)
* Connect to Vddd when CCB IF (SP=H) is to be used.
39 RD I Input
Read control signal input pin (parallel IF)
* Connect to Vddd when CCB IF (SP=H) is to be used.
40 A0/CL I Input
CL input pin (CCB IF)/ address input pin 0 (parallel IF)
41 A1/CE I Input
CE input pin (CCB IF)/ address input pin 1 (parallel IF)
42 A2/DI I Input
DI input pin (CCB IF)/ address input pin 2 (parallel IF)
43 A3 I Input
Address input pin 3 (parallel IF)
* Connect to Vssd when CCB IF (SP=H) is to be used.
44 CS I Input
Chip selector input pin (parallel IF)
* Connect to Vddd when CCB IF (SP=H) is to be used.
45 STNBY I Input
Standby mode input pin (H: standby)
46 RST I Input
System reset input pin (L: reset)
47 SP I Input
CCB/parallel setting input pin (H: CCB, L: parallel)
48 BUSWD I Input
Data bus width setting input pin (L: 8 bits, H: 16 bits)
49 TIN I Input
Test input pin (This pin must be connected to Vssd.)
50 NC - -
NC pin (This pin must be open.)
51 Vssa - -
Analog GND pin
52 Vref AO Vdda/2
Reference voltage output pin (Vdda/2)
53 MPXIN AI Input
Baseband (multiplex) signal input pin
54 Vdda - -
Analog power pin
55 FLOUT AO Vdda/2
Subcarrier output pin (76kHz BPF output)
56 CIN AI Input
Subcarrier input pin (comparator input)
57 NC - -
NC pin (This pin must be open.)
58 TPC1 I Input
Test input pin (This pin must be connected to Vssd.)
59 TPC2 I Input
Test input pin (This pin must be connected to Vssd.)
60 TEST I Input
Test mode setting pin (This pin must be connected to Vssd.)
61 TOSEL1 I Input
Test input pin (This pin must be connected to Vssd.)
62 TOSEL2 I Input
Test input pin (This pin must be connected to Vssd.)
63 Vssd - -
Digital GND pin
64 XIN I Oscillation
System clock pin (crystal oscillator/external clock input)
LC72717PW
www.onsemi.com
8
Internal Equivalent Circuit of Analog Pins
Name of pin
Pin number in parentheses
Internal equivalent circuit
MPXIN(53)
FLOUT(55)
CIN(56)
Vref(52)
+
-
+
-
Vref
Vdda
Vssa
LC72717PW
www.onsemi.com
9
CPU Interface <CCB Mode>
CCB (Computer Control Bus), which is the ON Semiconductor original serial bus format for ON Semiconductor’s
acoustic LSIs, performs data input and output.
The CCB address is transmitted with CE= “L”, acknowledging the CCB I/O mode when CE is set to “H”.
(1) List of CCB modes
CCB address
I/O mode Description
Hexadecimal B0 B1 B2 B3 A0 A1 A2 A3
FAh 0 1 0 1 1 1 1 1 Input
16-bit control data input
FBh 1 1 0 1 1 1 1 1 Output
Output of data corresponding to the
input clock (CL) portion
FCh 0 0 1 1 1 1 1 1 Input
Layer 4 CRC check circuit data input
(on the 8-bit units)
Fad 1 0 1 1 1 1 1 1 Output
Output of the register only
(2) Data input (CCB address FAh)
This is to set data to the LSI internal register. DI input includes both CCB address FAh and 16-bit data (DI0 to
DI15) are input.
Assignment of each bit is as shown in the table below. Though DI12 to DI15 are invalid data, it is necessary to enter
the arbitrary data so that the total of 16 bits can be obtained. For the contents of each register and register address,
refer to the chapter of CPU registers.
(Note that writing into the layer 4 CRC check register will be described later (for the CCB address, use FCh.))
(3) Output of the corrected data (CCB address FBh)
The corrected packet data is output from LSI. The CCB address, FBh, is input in DI.
The valid data to be output is maximum 288 bits. If the clock input (CL input) is interrupted halfway to set CE to the
“L” level, data output is not troubled by the next interrupt.
The maximum data to be output is 288 bits (36 bytes) and the leading two bytes, to which the status register
(STAT) contents and the block number register (BLNO) contents are added, are output.
STAT and BLNO, which are the register contents outputs, are output respectively with LSB first.
The corrected data is output sequentially beginning with the leading bit in data of one block.
The BIC code is not output.
In case of data reading for multiple times by one interrupt signal (INT), the output data is not guaranteed.
STAT (8) BLN0 (8) Data block (176) Error-corrected data Layer 2 CRC (14) Parity (82)
7OD to 0OD 15OD to 8OD 16OD to 191OD 205OD to 192OD 287OD to 206OD
(LSB) Input data (8-bit) (MSB) Register address Invalid data
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 to DI15
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT0 BIT1 BIT2 BIT3 BIT4 to BIT7
DI0
B0
B1
B2
B3 A0
A1
A2
A3
DI1
DI13 DI14
DI15
tCH
tCL
CE
CL
DI
Internal data latch
tSU
tHD
tEL
tES
tLC
tEH
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

LC72717PW-H

Mfr. #:
Buy LC72717PW-H
Manufacturer:
ON Semiconductor
Description:
RF Receiver DARC DECODE-LSI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet