LC72717PW
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4
BUSWD
SP
RST
STNBY
CS
A3
A2/DI
A1/CE
A0/CL
RD
WR
DO
Vssd
Vddd
INT
Block Diagram
Vssa
Vre
f
MPXIN
Vdda
FLOUT
CIN
Vssd
XIN
XOUT
Vddd
IOCNT1
IOCNT2
CLK16
DATA
FLOCK
BLOCK
FCK
BCK
CRC4
DREQ
DACK
Vssd
Vddd
RDY
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Anti-
aliasing filter
76kHz
BPF(SCF)
Reference
voltage
Divider
2T Delay
1T Delay
LPF
MSK correction
circuit
LPF
PN
demodulation
+
-
Vref
Parallel IF
CCB IF
Frame
memory
Error correction
and
Layer 2 CRC
Timing
control
Internal clock
Output control
and
CPU register
Clock
regeneration
Synchronization
regeneration
Layer 4
CRC
LC72717PW
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5
Package Dimensions
unit : mm
SPQFP64 10x10 / SQFP64
CASE 131AK
ISSUE A
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
GENERIC MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
XXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
XXXXXXXX
YDD
10.0±0.1
12
0.5
(1.25)
0.10
10.0±0.1
12.0
±
0.2
12.0±0.2
64
0.18
+0.08
0.03
0.10
1.7 MAX
(1.5)0.1±0.1
0 to10°
0.5±0.2
0.15±0.05
(Unit: mm)
11.40
11.40
0.280.50
1.00
SOLDERING FOOTPRINT*
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
LC72717PW
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6
Pin Assignment
List of Pin Functions
Pin No. Name of Pin IO Form State with RST=”L” Description of Functions
1 XOUT O Oscillation
Pin for system clock (crystal oscillator)
2 Vddd - -
Digital power pin
3 IOCNT1 I Input
Data bus I/O control 1 input pin (Parallel IF)
* Connect to Vssd when CCB IF (SP=H) is to be used.
4 IOCNT2 I Input
Data bus I/O control 2 input pin (Parallel IF)
* Connect to Vssd when CCB IF (SP=H) is to be used.
5 CLK16 O L
Clock regeneration monitor pin
6 DATA O L
Demodulation data monitor pin
7 FLOCK O L
Frame synchronization flag output pin (H: synchronized)
8 BLOCK O L
Block synchronization flag output pin (H: synchronized)
9 FCK O L
Frame start signal output pin
10 BCK O L
Block start signal output pin
11 CRC4 O H
Layer 4 CRC check result output pin
12 DREQ O H
DMA REQ signal output pin (parallel IF)
13 DACK I Input
DMA ACK signal input pin (parallel IF)
* Connect to Vddd when CCB IF (SP=H) is to be used.
14 Vssd - -
Digital GND pin
15 Vddd - -
Digital power pin
16 RDY O H
Read data READY signal output pin (parallel IF)
Continued on next page.
Top view
BUSWD
SP
RST
STNBY
CS
A3
A2/DI
A1/CE
A0/CL
RD
WR
NC
DO
Vssd
Vddd
INT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TIN
NC
Vssa
Vref
MPXIN
Vdda
FLOUT
CIN
NC
TPC1
TPC2
TEST
TOSEL1
TOSEL2
Vssd
XIN
LC72717PW
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XOUT
Vddd
IOCNT1
IOCNT2
CLK16
DATA
FLOCK
BLOCK
FCK
BCK
CRC4
DREQ
DACK
Vssd
Vddd
RDY

LC72717PW-H

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
RF Receiver DARC DECODE-LSI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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