Si4702/03-D30
10 Rev. 0.6
Table 7. 2-Wire Control Interface Characteristics
1,2,3
(V
D
=V
A
= 2.7 to 5.5 V, V
IO
= 1.62 to 3.6 V, T
A
= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
SCLK Frequency f
SCL
0—400kHz
SCLK Low Time t
LOW
1.3 µs
SCLK High Time t
HIGH
0.6 µs
SCLK Input to SDIO
Setup
(START)
t
SU:STA
0.6 µs
SCLK Input to SDIO
Hold (START) t
HD:STA
0.6 µs
SDIO Input to SCLK
Setup t
SU:DAT
100 ns
SDIO Input to SCLK
Hold
4,5
t
HD:DAT
0—900ns
SCLK input to SDIO
Setup (STOP) t
SU:STO
0.6 µs
STOP to START Time t
BUF
1.3 µs
SDIO Output Fall Time t
f:OUT
20 + 0.1 C
b
—250ns
SDIO Input, SCLK Rise/Fall Time t
f:IN
t
r:IN
20 + 0.1 C
b
—300ns
SCLK, SDIO Capacitive Loading C
b
——50pF
Input Filter Pulse Suppression t
SP
50 ns
Notes:
1. When V
IO
= 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the 1st start condition.
3. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST
.
4. As a 2-wire transmitter, the Si4702/03-D30 delays SDIO by a minimum of 300 ns from the V
IH
threshold of SCLK to
comply with the 0 ns t
HD:DAT
specification.
5. The maximum t
HD:DAT
has only to be met when f
SCL
= 400 kHz. At frequencies below 400 KHz, t
HD:DAT
may be
violated so long as all other timing parameters are met.
Si4702/03-D30
Rev. 0.6 11
Figure 5. 2-Wire Control Interface Read and Write Timing Parameters
Figure 6. 2-Wire Control Interface Read and Write Timing Diagram
SCLK
70%
30%
SDIO
70%
30%
START
STARTSTOP
t
f:IN
t
r:IN
t
LOW
t
HIGH
t
HD:STA
t
SU:STA
t
SU:STO
t
SP
t
BUF
t
SU:DAT
t
r:IN
t
HD:DAT
t
f:IN,
t
f:OUT
SCLK
SDIO
START STOPADDRESS + R/W ACK DATA ACK DATA ACK
A6-A0,
R/W
D7-D0 D7-D0
Si4702/03-D30
12 Rev. 0.6
Table 8. FM Receiver Characteristics
1,2
(V
D
=V
A
= 2.7 to 5.5 V, V
IO
= 1.62 to 3.6 V, T
A
= –20 to 85 °C, 76–108 MHz)
Parameter Symbol Test Condition Min Typ Max Unit
Input Frequency f
RF
64 108 MHz
Sensitivity
3,4,5,6,7
(S+N)/N = 26 dB 1.7 3.5 µVEMF
Sensitivity (50 matching
network)
3,4,5,6,8
(S+N)/N = 26 dB 1.1 µVEMF
RDS Sensitivity
8
f=2kHz,
RDS BLER < 5%
15 µVEMF
LNA Input Resistance
8,9
345k
LNA Input Capacitance
8,9
456pF
Input IP3
8,10
103 108 dBµVEMF
AM Suppression
3,4,5,8,9
m = 0.3 40 55 dB
Adjacent Channel Selectivity ±200 kHz 35 50 dB
Alternate Channel Selectivity ±400 kHz 60 70 dB
Spurious Response Rejection
8
In-band 35 dB
RCLK Frequency
8
32.768 kHz
RCLK Frequency Tolerance
8,11
Frequency Spacing = 100
or 200 kHz
–200 200
ppm
Frequency
Spacing = 50 kHz
–50 50
Audio Output Voltage
3,4,5,9
72 80 90 mV
RMS
Audio Output L/R Imbalance
3,4,9,12
—— 1 dB
Audio Frequency Response Low
8
–3 dB 30 Hz
Audio Frequency Response High
8
–3 dB 15 kHz
Notes:
1. Additional testing information is available in "AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure".
Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN383: Si47xx
Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
3. F
MOD
= 1 kHz, 75 µs de-emphasis
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. B
AF
= 300 Hz to 15 kHz, A-weighted.
7. Typical sensitivity with headphone matching network.
8. Guaranteed by characterization.
9. V
EMF
=1mV.
10. |f
2
– f
1
| > 1 MHz, f
0
=2xf
1
– f
2
. AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page 23.
11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 23. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing.
12. f = 75 kHz.
13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 23.
14. RDS high-performance mode enabled RDSPRF 06h[9] = 1. Refer to 6. "Register Descriptions" on page 23.
15. At LOUT and ROUT pins.
16. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powerup
time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is
complete. See "AN230: Si4700/01/02/03 Programming Guide" for more information.
17. Minimum and maximum at room temperature (25 °C).

SI4702-D30-GM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
RF RCVR FM 76MHZ-108MHZ 20QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet