Si4702/03-D30
Rev. 0.6 7
Figure 2. Reset Timing Parameters for Busmode Select Method 2 (GPIO3 = 1)
Table 5. Reset Timing Characteristics (Busmode Select Method 2)
1,2,3
Parameter Symbol Test Condition Min Typ Max Unit
GPIO1 and GPIO3 Setup to RST
t
SRST2
GPIO3 = 1 30 ns
GPIO1 and GPIO3 Hold from R
ST t
HRST2
30 ns
Notes:
1.
When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST
.
2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST
.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
70%
30%
t
SRST2
RST
t
HRST2
GPIO3
70%
30%
GPIO1
70%
30%
Si4702/03-D30
8 Rev. 0.6
Figure 3. 3-Wire Control Interface Write Timing Parameters
Table 6. 3-Wire Control Interface Characteristics
(V
D
=V
A
= 2.7 to 5.5 V, V
IO
= 1.62 to 3.6 V, T
A
= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
SCLK Frequency f
CLK
0—2.5MHz
SCLK High Time t
HIGH
25 ns
SCLK Low Time t
LOW
25 ns
SDIO Input, SEN
to SCLKSetup t
S
20 ns
SDIO Input to SCLKHold t
HSDIO
10 ns
SEN
Input to SCLKHold t
HSEN1
10 ns
SEN
Input to SCLKHold t
HSEN2
10 ns
SCLKto SDIO Output Valid t
CDV
Read 2 25 ns
SCLKto SDIO Output High Z t
CDZ
Read 2 25 ns
Note: When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST
.
Si4702/03-D30
Rev. 0.6 9
Figure 4. 3-Wire Control Interface Read Timing Parameters
½ Cycle Bus
Turnaround
SCLK
70%
30%
SEN
70%
30%
SDIO
80%
20%
t
HSDIO
t
CDV
t
CDZ
Address In Data Out
A7 A0
A6-A5,
R/W,
A4-A1
D15 D14-D1 D0
t
S
t
S
t
HSEN1
t
HSEN2

SI4702-D30-GM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
RF RCVR FM 76MHZ-108MHZ 20QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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