Si4702/03-D30
Rev. 0.6 19
4.8.2. 2-wire Control Interface
For two-wire operation, the SCLK and SDIO pins
function in open-drain mode (pull-down only) and must
be pulled up by an external device. A transfer begins
with the START condition (falling edge of SDIO while
SCLK is high). The control word is latched internally on
rising SCLK edges and is eight bits in length, comprised
of a seven bit device address equal to 0010000b and a
read/write bit (write = 0 and read = 1).
The device acknowledges the address by driving SDIO
low after the next falling SCLK edge, for 1 cycle. For
write operations, the device acknowledge is followed by
an eight bit data word latched internally on rising edges
of SCLK. The device acknowledges each byte of data
written by driving SDIO low after the next falling SCLK
edge, for 1 cycle. An internal address counter
automatically increments to allow continuous data byte
writes, starting with the upper byte of register 02h,
followed by the lower byte of register 02h, and onward
until the lower byte of the last register is reached. The
internal address counter then automatically wraps
around to the upper byte of register 00h and proceeds
from there until continuous writes end. Data transfer
ends with the STOP condition (rising edge of SDIO
while SCLK is high). After every STOP condition, the
internal address counter is reset.
For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling
SCLK edges. An internal address counter automatically
increments to allow continuous data byte reads, starting
with the upper byte of register 0Ah, followed by the
lower byte of register 0Ah, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous reads cease. After each byte of data is read,
the controller IC must drive an acknowledge (SDIO = 0)
if an additional byte of data will be requested. Data
transfer ends with the STOP condition. After every
STOP condition, the internal address counter is reset.
For details on timing specifications and diagrams, refer
to Table 7, “2-Wire Control Interface
Characteristics
1,2,3
,” on page 10, Figure 5, “2-Wire
Control Interface Read and Write Timing Parameters,”
on page 11 and Figure 6, “2-Wire Control Interface
Read and Write Timing Diagram,” on page 11.
4.9. Reset, Powerup, and Powerdown
Driving the RST pin low will disable the Si4702/03-D30
and its control bus interface, and reset the registers to
their default settings. Driving the RST
pin high will bring
the device out of reset. As the device is brought out of
reset, it will sample the state of several pins to select
between 2-wire and 3-wire control interface operation,
using one of two busmode selection methods.
Busmode selection method 1 requires the use of the
GPIO3, SEN
, and SDIO pins. To use this busmode
selection method, the GPIO3 and SDIO pins must be
sampled low by the device on the rising edge of RST
.
The user may either drive the GPIO3 pin low externally,
or leave the pin floating. If the pin is not driven by the
user, it will be pulled low by an internal 1 M resistor
which is active only while RST
is low. The user must
drive the SEN
and SDIO pins externally to the proper
state.
To select 2-wire operation, the SEN
pin must be
sampled high by the device on the rising edge of RST
.
To select 3-wire operation, the SEN
pin must be
sampled low by the device on the rising edge of RST
.
Refer to Table 4, “Reset Timing Characteristics
(Busmode Select Method 1)
1,2,3
,” on page 6 and
Figure 1, “Reset Timing Parameters for Busmode
Select Method 1 (GPIO3 = 0),” on page 6.
Busmode selection method 2 requires only the use of
the GPIO3 and GPIO1 pins. This is the recommended
busmode selection method when not using the internal
crystal oscillator. To use this busmode selection
method, the GPIO3 pin must be sampled high on the
rising edge of RST
. The user must drive the GPIO3 pin
high externally, or pull it up with a resistor of 100 k or
less. The user must also drive the GPIO1 pin externally
to the proper state.
To select 2-wire operation, the GPIO1 pin must be
sampled high by the device on the rising edge of RST
.
To select 3-wire operation, the GPIO1 pin must be
sampled low by the device on the rising edge of RST
.
Refer to Table 5, “Reset Timing Characteristics
(Busmode Select Method 2)
1,2,3
,” on page 7 and
Figure 2, “Reset Timing Parameters for Busmode
Select Method 2 (GPIO3 = 1),” on page 7.
Table 9 summarizes the two bus selection methods.
