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TJA1022TK,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
TJA1022 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 3 — 24 May 2018 10 of 28
NXP Semiconductors
TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
If the voltage on pin V
BAT
drops below the LOW-level power-on reset threshold, V
th(POR)L
,
the TJA1022 switches to Reset mode (i.e. all output drivers are disabled and all inputs are
ignored). The TJA1022 switches to Sleep mode if V
BAT
> V
th(POR)H
.
7.6 Fail-safe features
Pin TXDx is pulled down to ground in order to force a predefined level on the transmit data
input if the pin is disconnected.
Pin SLPx_N is pulled down to ground to ensure the transceiver is forced to Sleep x mode
if SLPx_N is disconnected.
Pins RXD1 and RXD2 are set floating if V
BAT
is disconnected.
The current in the transmitter output stage is limited in order to protect the transmitter
against short circuits to pins V
BAT
or GND.
A loss of power (pins V
BAT
and GND) has no impact on the bus lines or on the
microcontroller. No reverse current will flow from the bus lines into the LINx pins. The
current path from V
BAT
to LINx via the integrated LIN slave termination resistors remains.
The TJA1022 can be disconnected from the power supply without influencing the LIN
busses.
The output drivers on pins LIN1 and LIN2 are protected against overtemperature
conditions. If the junction temperature exceeds the shutdown junction temperature, T
j(sd)
,
the thermal protection circuit disables the output drivers. The drivers are enabled again
when the junction temperature falls below T
j(sd)
and pin TXDx is HIGH.
The initial TXD dominant check prevents the bus being driven to a permanent dominant
state (blocking all network communications) if pin TXDx is forced permanently LOW by a
hardware and/or software application failure. The input level on TXDx is checked after a
transition to Normal mode. If TXDx is LOW, the transmit path will remain disabled and will
only be enabled when TXDx goes HIGH.
Once the transmitter has been enabled, a TXD dominant time-out timer is started every
time pin TXDx goes LOW. If the LOW state on pin TXDx persists for longer than the
TXD dominant time-out time (t
to(dom)TXD
), the transmitter is disabled, releasing the bus
line to recessive state. The TXD dominant time-out timer is reset when pin TXDx goes
HIGH.
TJA1022 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 3 — 24 May 2018 11 of 28
NXP Semiconductors
TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
8. Limiting values
[1] Equivalent to discharging a 150 pF capacitor through a 330 resistor.
[2] Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor.
[3] Equivalent to discharging a 200 pF capacitor through a 10 resistor and a 0.75 H coil.
[4] Junction temperature in accordance with IEC 60747-1. An alternative definition is: T
j
=T
amb
+P R
th(j-a)
, where R
th(j-a)
is a fixed value.
The rating for T
vj
limits the allowable combinations of power dissipation (P) and ambient temperature (T
amb
).
9. Thermal characteristics
[1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board.
[2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND, unless
otherwise specified. Positive currents flow into the IC.
Symbol Parameter Conditions Min Max Unit
V
BAT
battery supply voltage 0.3 +42 V
V
TXD
voltage on pin TXD pins TXD1 and TXD2 0.3 +7 V
V
RXD
voltage on pin RXD pins RXD1 and RXD2 0.3 +7 V
V
SLP_N
voltage on pin SLP_N pins SLP1_N and SLP2_N 0.3 +7 V
V
LIN
voltage on pin LIN pins LIN1 and LIN2; with respect to
GND and V
BAT
42 +42 V
V
(LIN1-LIN2)
voltage difference between pin
LIN1 and pin LIN2 (absolute
value)
-42 V
V
ESD
electrostatic discharge voltage
according to IEC 61000-4-2 on pins LIN1, LIN2 and V
BAT
[1]
8+8 kV
human body model on pins LIN1, LIN2 and V
BAT
[2]
8+8 kV
on pins TXD1, TXD2, RXD1, RXD2,
SLP1_N and SLP2_N
[2]
2+2 kV
charge device model all pins 750 +750 V
machine model all pins
[3]
200 +200 V
T
vj
virtual junction temperature
[4]
40 +150 C
T
stg
storage temperature 55 +150 C
Table 7. Thermal characteristics
According to IEC 60747-1.
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to ambient SO14 package
[1]
145 K/W
HVSON14 package
[2]
50 K/W
DHVQFN24 package
[2]
42.7 K/W
TJA1022 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 3 — 24 May 2018 12 of 28
NXP Semiconductors
TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
10. Static characteristics
Table 8. Static characteristics
V
BAT
= 5 V to 18 V; T
vj
=
40
C to +150
C; R
L(LIN-VBAT)
= 500
; all voltages are referenced to pin GND; positive currents
flow into the IC; typical values are given at V
BAT
= 12 V; unless otherwise specified.
[1]
Symbol Parameter Conditions Min Typ Max Unit
Supply
V
BAT
battery supply voltage 5 - 18 V
I
BAT
battery supply current Sleep mode (both channels);
bus recessive (both channels);
V
LINx
=V
BAT
; V
SLPx_N
=0V
2.5 7 10 A
Sleep mode (both channels);
bus dominant (both channels);
V
LINx
=0V; V
SLPx_N
=0V;
V
BAT
=12V
300 800 3200 A
Standby mode (both channels);
bus recessive (both channels);
V
LINx
=V
BAT
; V
SLPx_N
=0V
2.5 7 10 A
Standby mode (both channels);
bus dominant (both channels);
V
LINx
=0V; V
SLPx_N
=0V;
V
BAT
=12V
200 600 2000 A
Normal mode (both channels);
bus recessive (both channels);
V
TXDx
=5 V; V
LINx
=V
BAT
;
V
SLPx_N
=5V
300 1600 3200 A
Normal mode (both channels);
bus dominant (both channels);
V
TXDx
=0 V; V
SLPx_N
=5V;
V
BAT
= 12 V
1410mA
Undervoltage reset
V
th(POR)L
LOW-level power-on reset
threshold voltage
power-on reset 1.6 3.1 3.9 V
V
th(POR)H
HIGH-level power-on reset
threshold voltage
2.3 3.4 4.3 V
V
hys(POR)
power-on reset hysteresis
voltage
[2]
0.05 0.3 1 V
V
th(VBATL)L
LOW-level V
BAT
LOW
threshold voltage
3.9 4.4 4.7 V
V
th(VBATL)H
HIGH-level V
BAT
LOW
threshold voltage
4.2 4.7 4.9 V
V
hys(VBATL)
V
BAT
LOW hysteresis
voltage
[2]
0.15 0.3 0.6 V
Pins TXDx and SLPx_N
V
IH
HIGH-level input voltage 2 - 7 V
V
IL
LOW-level input voltage 0.3 - +0.8 V
V
hys
hysteresis voltage
[2]
50 200 400 mV
R
pd
pull-down resistance on TXDx 50 125 325 k
on SLPx_N 100 250 650 k
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TJA1022TK,118

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Buy TJA1022TK,118
Manufacturer:
NXP Semiconductors
Description:
LIN Transceivers DUAL LIN 5-18V
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