NJM2211M Datasheet NJM2211M, NJM2211D | P7-P9

NJM2211

-7-

Ver.2003-12-09

■ APPLICATIONS

FSK Decoding

Figure 2 shows the basic circuit connection for FSK decoding. With reference to Figures 1 and 2, the functions of

external components are defined as follows : R0 and C0 set the PLL center frequency. R1 sets the system bandwidth,

and C1 sets the loop filter time constant and the loop damping factor. C

and R

from a one pole post-detection filter for

the FSK data output. The resistor R

(=510kΩ) from pin 7 to pin 8 introduces positive feedback across FSK comparator

to facilitate rapid transition between output logic states.

Recommended component values for some of the most commonly used FSK bauds are given in Table 1.

Design Instructions

The circuit of Figure 2 can be tailored for any FSK decoding application by the choice of five key circuit components ;

R0, R1, C0, C1 and CF. For a given set of FSK mark and space frequencies. f1 and f2, these parameters can be

calculated as follows :

1. Calculate PLL center frequency, f

2. Chose a value of timing resistor R0 to be in the range of 10kΩ to 100kΩ. This choice is arbitary. The recommended

value is R0

≅ 20kΩ. The final value of R0 is normally fine-tuned with the series potentiometer, R

3. Calculate value of C0 from Design Equation No.1 or from Typical Performance Characteristics :

C0=1 / R0f

4. Calculate R1 to give a ∆f equal to the mark-space deviation :

R1=R0 [f

/ (f

- f

)]

5. Calculate C1 to set loop damping. (See Design Equation No.4.)

Normally, ξ ≈ 1 / 2 is recommended

Then :C1=C0 / 4 for ξ =1 / 2

6. Calculate Data Filter Capacitance, C

For R

=100kΩ. R

=510kΩ, the recommended value of C

is :

RateBand

)Fµin(C

Note : All calculated component values except R0 can be rounded off to the nearest standard value, and R0 can be varied to fine-tune center

frequency through a series potentiometer, R

(see Figure 2).

Table 1. Recommended Value for FSK

(Ref. Fig. 2)

FSK Band Component Values

300 Band C0=0.039µF C

=0.005µF

=1070Hz C1=0.01µF R0=18kΩ

f2 =1270Hz R1=100kΩ

300 Band C0=0.022µF C

=0.005µF

=2025Hz C1=0.0047µF R0=18kΩ

=2225Hz R1=200kΩ

1200 Band C0=0.027µF C

=0.0022µF

=1200Hz C1=0.01µF R0=18kΩ

=2200Hz R1=30kΩ

Figure 2. FSK Decoding

NJM2211

Ver.2003-12-09

Figure 3. FSK Demodulation with Carrier Detect Capability Figure 4. Tone Detection

Design Example

75 Band FSK demodulator with mark / space frequencies of 1110 / 1170Hz :

Step 1 : Calculate f

=(1110+1170) (1 / 2)=1140Hz

Step 2 : Choose R0=20kΩ (18kΩ fixed resistor in series with 5kΩ potentiometer)

Step 3 : Calculate C0 from VCO Frequency vs. Timing Capacitor : C0 =0.044µF

Step 4 : Calculate R1 : R1=R0 (1140 / 60) =380kΩ

Step 5 : Calculate C1 : C1=C0 / 4=0.011µF

Note : All values except R0 can be rounded off to nearest standard value.

FSK Decoding With Carrier Detect

The lock-detect section of the NJM2211 can be used as a carrier detect option for FSK decoding. The recommended

circuit connection for this application is shown in Figure 3. The open-collector lock-detect output, pin 6, is shorted to the

data output (pin 7). Thus, the data output will be disabled at "low" state, until there is a carrier within the detection band of

the PLL, and the pin 6 output goes "high" to enable the data output.

The Minimum value of the lock-detect filter capacitance C

is inversely proportional to the capture range, ±∆f

. This is

the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. It is

further limited by C1. For most applications, ∆f

<∆f / 2, For R

=470kΩ, the approximate minimum value of C

can be

determined by :

(µF) ≥ 16 / capture range in Hz

With values of C

that are too small, chatter can be observed on the lock-detect output as an incoming signal

frequency approaches the capture bandwidth. Excessively large values of C

will slow the response time of the

lock-detect output.

Tone Detection

Figure 4 shows the generalized circuit connection for tone detection. The logic outputs, Q and

at pins 5 and 6 are

normally at "high" and "low" logic states, respectively. When a tone is present within the detection band of the PLL, the

logic state at these outputs becomes reversed for the duration of the input tone. Each logic output can sink 5mA of load

current.

Both logic outputs at pins 5 and 6 are open-collector type stages, and require external pull-up resistors R

and R

shown in Figure 4.

With reference to Figure 1 and 4, the function of the external circuit components can be explained as follows : R0 and

C0 set VCO center frequency, R1 sets the detection bandwidth, C1 sets the lowpass-loop filter time constant and the

loop damping factor, and R

and R

are the respective pull-up resistors for the Q and

logic outputs.

NJM2211

Ver.2003-12-09

Design Instructions

The circuit of Figure 4 can be optimized for any tone-detection application by the choice of five key circuit

components : R0, R1, C0, C1, and C

. For a given input tone frequency, f

, these parameters are calculated as follows :

1. Chose R0 to be in the range of 15kΩ to 100kΩ. This choice is arbitrary.

2. Calculate C0 to set center frequency, f

equal to f

: C0=1 / R0fs.

3. Calculate R1 to set bandwidth ±∆f (see Design Equation No.5) : R1=R0 (f

/ ∆f)

Note : The total detection bandwidth covers the frequency range of f

=∆f

4. Calculate value of C1 for a given loop damping factor :

C1=C0 / 16ξ

Normally ξ ≈ 1 / 2 is optimum for most tone-detector applications, giving C1=0.25 C0.

Increasing C1 improves the out-of band signal rejection, but increases the PLL capture time.

5. Calculate value of filter capacitor C

. To avoid chatter at the logic output, with R

=470kΩ, C

must be :

(µF) ≥ (16 / capture range in Hz)

Increasing C

slows the logic output response time.

Design Examples

Tone detector with a detection band of 1kHz±20Hz :

Step 1 : Choose R0=20kΩ (18kΩ in series with 5kΩ potentiometer).

Step 2 : Choose C0 for f

=1kHz : C0 =0.05µF.

Step 3 : Calculate R1 : R1=(R0)(1000 / 20)=1MΩ.

Step 4 : Calculate C1 : for ξ=1 / 2, C1=0.25µF, C2=0.013µF.

Step 5 : Calculate C

: C

=16 / 38=0.42µF.

Step 6 : Fine tune the center frequency with the 5kΩ potentiometer, R

Linear FM Detection

The NJM2211 can be used as a linear FM detector for a wide range of analog communications and telemetry

applications. The recommended circuit connection for the application is shown in Figure 5. The demodulated output is

taken from the loop phase detector output (pin 11), through a post detection filter made up of R

and C

, and an external

buffer amplifier. This buffer amplifier is necessary because of the high impedance output at pin 11. Normally, a

non-inverting unity gain op amp can be used as a buffer amplifier, as shown in Figure 5.

Figure 5. Linear FM Detector

The FM detector gain, i.e., the output voltage change per unit of FM deviation, can be given as :

OUT

=R1 V

/100 R0 Volts/% deviation

where V

is the internal reference voltage. For the choice of extrernal components R1, R0, C

, C1 and C

, see the

section on Design Equations.

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