CY7B9945V RoboClock
®
High-Speed Multi-Phase PLL Clock Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07336 Rev. *N Revised April 7, 2017
High-Speed Multi-Phase PLL Clock Buffer
Features
■ 500 ps max Total Timing Budget (TTB™) window
■ 24 MHz–200 MHz input and Output Operation
■ Low Output-output skew <200 ps
■ 10 + 1 LVTTL outputs driving 50 terminated lines
■ Dedicated feedback output
■ Phase adjustments in 625 ps/1300 ps steps up to +10.4 ns
■ 3.3-V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable
Reference Inputs
■ Multiply or Divide Ratios of 1 through 6, 8, 10, and 12
■ Individual Output Bank Disable
■ Output High Impedance Option for Testing Purposes
■ Integrated Phase Locked Loop (PLL) with Lock Indicator
■ Low Cycle-cycle jitter (<100 ps peak-peak)
■ 3.3 V Operation
■ Industrial Temperature Range: –40 °C to +85 °C
■ 52-pin 1.4 mm TQFP package
Functional Description
The CY7B9945V high-speed multi-phase PLL clock buffer offers
user selectable control over system clock functions. This multiple
output clock driver provides the system integrator with functions
necessary to optimize the timing of high performance computer
and communication systems.
The device features a guaranteed maximum TTB window
specifying all occurrences of output clocks. This includes the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50 while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
enable a divide function of 1 to 12, with phase adjustments in
625 ps–1300 ps increments up to ±10.4 ns. The dedicated
feedback output enables divide-by functionality from 1 to 12 and
limited phase adjustments. However, if needed, any one of the
ten outputs can be connected to the feedback input as well as
driving other inputs.
Selectable reference input is a fault tolerant feature that enables
smooth change over to a secondary clock source when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
For a complete list of related documentation, click here.
PLL
FBK
QF
2Q0
2Q1
2Q2
2Q3
Divide
and
Phase
Select
DIS2
LOCK
FS
1Q0
1Q1
1Q2
1Q3
Divide
and
Phase
Select
3
3
2F0
2F1
3
3
2DS0
2DS1
Divide
and
Phase
Select
3
FBF0
3
3
FBDS0
FBDS1
DIS1
REFA-
REFA+
REFB-
REFB+
3
3
3
1F0
1F1
3
3
1F2
1F3
3
3
1DS0
1DS1
2Q4
2Q5
REFSEL
MODE
