Document Number: 38-07336 Rev. *N Page 8 of 18
Output Disable Description
The output of each output bank can be independently put into a
HOLD OFF or high impedance state. The combination of the
MODE and DIS[1:2] inputs determines the clock outputs’ state
for each bank. When the DIS[1:2] is LOW, the outputs of the
corresponding banks are enabled. When DIS[1:2] is HIGH, the
outputs for that bank are disabled to a high impedance (HI-Z) or
HOLD OFF state. Table 5 defines the disabled outputs functions.
The HOLD OFF state is a power saving feature. An output bank
is disabled to the HOLD OFF state in a maximum of six output
clock cycles from the time the disable input is HIGH. When
disabled to the HOLD OFF state, outputs are driven to a logic
LOW state on their falling edges. This makes certain that the
output clocks are stopped without a glitch. When a bank of
outputs is disabled to HI-Z state, the respective bank of outputs
go High-Z immediately.
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit t
PD
.
When in the locked state, after four or more consecutive
feedback clock cycles with phase errors, the LOCK output is
forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase errorless
feedback clock cycles are required to enable the LOCK output to
indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH, a
“Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW. This
time out period is based upon a divided down reference clock.
This assumes that there is activity on the selected REF input. If
there is no activity on the selected REF input then the LOCK
detect pin does not accurately reflect the state of the internal
PLL.
Factory Test Mode Description
The device enters factory test mode when the MODE is driven
to MID. In factory test mode, the device operates with its internal
PLL disconnected; input level supplied to the reference input is
used in place of the PLL output. In TEST mode the FB input is
tied LOW. All functions of the device remain operational in
factory test mode except the internal PLL and output bank
disables. The MODE input is designed as a static input. Dynam-
ically toggling this input from LOW to HIGH temporarily causes
the device to go into factory test mode (when passing through
the MID state).
When in the test mode, the device is reset to a deterministic state
by driving the DIS2 input HIGH. Doing so disables all outputs
and, after the selected reference clock pin has five positive
transitions, all internal finite state machines (FSM) are set at a
deterministic state. The states depend on the configurations of
the divide, skew and frequency selection. All clock outputs stay
in High-Z mode and all FSMs stay in the deterministic state until
DIS2 is deasserted. This causes the device to reenter factory
test mode.
Safe Operating Zone
Figure 3 shows the operating condition of the device not
exceeding its allowable maximum junction temperature of
150°C. Figure 3 shows the maximum number of outputs that can
operate at 185 MHz (with 25 pF load and no air flow) or 200 MHz
(with 10-pF load and no air flow) at various ambient
temperatures. At the limit line, all other outputs are configured to
divide-by-two (i.e., operating at 92.5 MHz) or lower frequencies.
The device operates below maximum allowable junction
temperature of 150°C when its configuration (with the specified
constraints) falls within the shaded region (safe operating zone).
Figure 3 shows that at 85°C, the maximum number of outputs
that can operate at 200 MHz is 6.
Figure 3. Typical Safe Operating Zone
Table 5. DIS[1:2] Functionality
MODE DIS[1:2] 1Q[0:3], 2Q[0:5]
HIGH/LOW LOW ENABLED
HIGH HIGH HI-Z
LOW HIGH HOLD-OFF
MID X FACTORY TEST
Typical Safe Operating Zone
(25-pF Load, 0-m/s air flow)
50
55
60
65
70
75
80
85
90
95
100
246810
Number of Outputs at 185 MHz
Ambient Temperature (C)
