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CY7B9945V-2AXCT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CY7B9945V RoboClock
®
Document Number: 38-07336 Rev. *N Page 4 of 18
Pin Definitions
Pin Name I/O Type Description
34 FS Input Three level
Input
Frequency Select. This input must be set according to the nominal
frequency (f
NOM
). See Table 1.
40, 39, 36, 37 REFA+,
REFA-,
REFB+,
REFB-
Input LVTTL/
LVDIFF
Reference Inputs. These inputs can operate as differential PECL or
single-ended TTL reference inputs to the PLL. When operating as a
single-ended LVTTL input, the complementary input is left open.
38 REFSEL Input LVTTL Reference Select Input. The REFSEL input controls the configuration of
reference input When LOW, it uses the REFA pair as the reference input.
When HIGH, it uses the REFB pair as the reference input. This input has
an internal pull down.
42 FBK Input LVTTL Feedback Input Clock. The PLL operates such that the rising edges of
the reference and feedback signals are aligned in phase and frequency.
This pin provides the clock output QF feedback to the phase detector.
28, 18, 35, 17, 2,
1
1F[0:3],
2F[0:1]
Input Three level
Input
Output Phase Function Select. Each pair determines the phase of the
respective bank of outputs. See Table 3.
19, 26 DIS[1:2] Input LVTTL Output Disable. Each input controls the state of the respective output
bank. When HIGH, the output bank is disabled to HOLD-OFF or High-Z
state; the disable state is determined by MODE. When LOW, outputs
1Q[0:3] and 2Q[0:5] are enabled. See Ta b le 5.
14, 12, 13, 3 [1:2]DS[0:1] Input Three level
Input
Output Divider Function Select. Each pair determines the divider ratio
of the respective bank of outputs. See Tab l e 4 .
29 FBF0 Input Three level
Input
Feedback Output Phase Function Select. This input determines the
phase of the QF output. See Table 3.
50, 51 FBDS[0:1] Input Three level
Input
Feedback Output Divider Function Select. This input determines the
divider ratio of the QF output. See Table 4.
48, 46, 32, 30, 5,
7, 8,10, 20, 22
1Q[0:3],
2Q[0:5]
Output LVTTL Clock Outputs with Adjustable Phases and f
NOM
Divide Ratios. The
output frequencies and phases are determined by [1:2]DS[0:1], and
1F[0:3] and 2F[0:1], respectively. See Table 3 and Ta b l e 4 .
44 QF Output LVTTL Feedback Clock Output. This output is connected to the FBK input. The
output frequency and phase are determined by FBDS[0:1] and FBF0,
respectively. See Table 3 and Table 4.
52 LOCK Output LVTTL PLL Lock Indicator. When HIGH, this output indicates that the internal
PLL is locked to the reference signal. When LOW, it indicates that the PLL
is attempting to acquire lock
25 MODE Input Three level
Input
This pin determines the clock outputs’ disable state. When this input
is HIGH, the clock outputs disables to high impedance state (High-Z).
When this input is LOW, the clock outputs disables to HOLD-OFF mode.
When in MID, the device enters factory test mode.
6, 9, 21, 31, 45,
47
VCCN PWR Power Supply for the Output Buffers
16, 27, 41 VCCQ PWR Power Supply for the Internal Circuitry
4, 11, 15, 23, 24,
33, 43, 49
GND PWR Device Ground
CY7B9945V RoboClock
®
Document Number: 38-07336 Rev. *N Page 5 of 18
Block Diagram Description
The PLL adjusts the phase and the frequency of its output signal
to minimize the delay between the reference (REFA/B+,
REFA/B-) and the feedback (FB) input signals.
The CY7B9945V has a flexible REF input scheme. These inputs
enable the use of either differential LVPECL or single ended
LVTTL inputs. To configure as single ended LVTTL inputs, leave
the complementary pin open (internally pulled to 1.5 V), then the
other input pin is used as a LVTTL input. The REF inputs are also
tolerant to hot insertion.
The REF inputs are changed dynamically. When changing from
one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget
(tMIN = tREF (nominal reference period) – tCCJ (cycle-cycle
jitter) – tPDEV (max. period deviation)) while reacquiring lock.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the
device. fNOM is directly related to the VCO frequency. The FS
setting for the device is shown in Ta b l e 1 . For CY7B9945V, the
upper fNOM range extends from 96 MHz to 200 MHz.
Time Unit Definition
Selectable skew is in discrete increments of time unit (t
U
). The
value of a t
U
is determined by the FS setting and the maximum
nominal output frequency. The equation determines the t
U
value
as follows:
t
U
= 1/(f
NOM
*N).
N is a multiplication factor that is determined by the FS setting.
f
NOM
is nominal frequency of the device. N is defined in Ta b l e 2 .
Table 1. Frequency Range Select
FS
[1]
f
NOM
(MHz)
Min Max
LOW 24 52
MID 48 100
HIGH 96 200
Table 2. N Factor Determination
FS
CY7B9945V
N f
NOM
(MHz) at which t
U
= 1.0 ns
LOW 32 31.25
MID 16 62.5
HIGH 8 125
Note
1. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
CY7B9945V RoboClock
®
Document Number: 38-07336 Rev. *N Page 6 of 18
Divide and Phase Select Matrix
The Divide Select Matrix is comprised of three independent
banks: two of clock outputs and one for feedback. The Phase
Select Matrix, enables independent phase adjustments on
1Q[0:1], 1Q[2:3] and 2Q[0:5]. The frequency of 1Q[0:3] is
controlled by 1DS[0:1] while the frequency of 2Q[0:5] is
controlled by 2DS[0:1]. The phase of 1Q[0:1] is controlled by
1F[0:1], that of 1Q[2:3] is controlled by 1F[2:3] and that of 2Q[0:5]
is controlled by 2F[0:1].
The high fanout feedback output buffer (QF) connects to the
feedback input (FBK).This feedback output has one phase
function select input (FBF0) and two divider function selects
FBDS[0:1].
The phase capabilities that are chosen by the phase function
select pins are shown in Ta b le 3 . The divide capabilities for each
bank are shown in Table 4.
Figure 2 on page 7 shows the timing relationship of program-
mable skew outputs. All times are measured with respect to REF
with the output used for feedback programmed with 0t
U
skew.
The PLL naturally aligns the rising edge of the FB input and REF
input. If the output used for feedback is programmed to another
skew position, then the whole t
U
matrix shifts with respect to REF.
For example, if the output used for feedback is programmed to
shift –4tU, then the whole matrix is shifted forward in time by 4tU.
Thus an output programmed with 4tU of skew gets effectively be
skewed 8t
U
with respect to REF.
Table 3. Output Phase Select
Control Signal Output Phase Function
1F1 1F0 1Q[0:1]
1F3 1F2 1Q[2:3]
2F1 2F0 2Q[0:5]
FBF0 QF
LOW LOW –4t
U
–4t
U
–8t
U
–4t
U
LOW MID –3t
U
–3t
U
–7t
U
N/A
LOW HIGH –2t
U
–2t
U
–6t
U
N/A
MID LOW –1t
U
–1t
U
BK1Q[0:1]
[2]
N/A
MID MID 0t
U
0t
U
0t
U
0t
U
MID HIGH +1t
U
+1t
U
BK1Q[2:3]
[2]
N/A
HIGH LOW +2t
U
+2t
U
+6t
U
N/A
HIGH MID +3t
U
+3t
U
+7t
U
N/A
HIGH HIGH +4t
U
+4t
U
+8t
U
+4t
U
Table 4. Output Divider Select
Control Signal Output Divider Function
[1:2]DS1
and FBDS1
[1:2]DS0
and
FBDS0
Bank1 Bank2 Feedback
LOW LOW / 1 / 1 / 1
LOW MID / 2 / 2 / 2
LOW HIGH / 3 / 3 / 3
MID LOW / 4 / 4 / 4
MID MID / 5 / 5 / 5
MID HIGH / 6 / 6 / 6
HIGH LOW / 8 / 8 / 8
HIGH MID / 10 / 10 / 10
HIGH HIGH / 12 / 12 / 12
Table 3. Output Phase Select (continued)
Control Signal Output Phase Function
Note
2. The level set on FS is determined by the “nominal” operating frequency (f
NOM
) of the V
CO
and Phase Generator. f
NOM
always appears on an output when the output
is operating in the undivided mode. The REF and FB are at f
NOM
when the output connected to FB is undivided.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CY7B9945V-2AXCT

Mfr. #:
Buy CY7B9945V-2AXCT
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 3.3V 200MHz 10 COM Programable
Lifecycle:
New from this manufacturer.
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