IGD616
Preliminary Data Sheet
Page 10 CT-Concept.com
Electrical Insulation Condition/Remark Min. Typ. Max. Units
Operating voltage For option T; continuous (note 6) 1500 V
DC
For option C; continuous (note 6) 600 1000 V
DC
Permitted d/dt (V
C*E*
) Ensured by design 100 V/ns
Test voltage 50 Hz/1 min (note 7) 4000 V
AC, eff
Partial discharge extinction volt. To IEC270 (note 8) 1700 V
AC, pk
Creep path primary-secondary Option T 19
mm
Option C 8 mm
Creep path secondary-secondary 19 mm
Footnotes
1) The unipolar primary supply voltage with a nominal value of V(VCC, GND) = 15.0V is multiplied by
a magnetic transformer, resulting in a unipolar secondary power supply voltage with a nominal
value of V(Cs, COM) = 16.4V. To provide a bipolar gate-driving voltage with the nominal values of
V(G, E) = +15.1V for turn-on and V(G, E) = - 15.1V for turn-off, both gate and emitter are
switched in full-bridge configuration via biploar junction transistors (providing a total nominal level
shift of 1.3V). The primary side is equipped with an automatic power-on reset which clears the
fault memories when the supply voltage approaches a specified limit with a maximum value of
13.5V.
2) In typical applications (hard-switching topology using recommended gate resistors and gate
charge) the switching frequency is primarily limited by the switching losses of the IGBT module or
by the gate power due to the gate charge required by the module. The switching losses of the
gate driver depend strongly on the particular operating conditions and increase with reducing the
gate resistance and increasing switching frequency.
For switching frequencies beyond 20kHz or
gate pulse charges > 5.1μC, the thermal limits of the gate driver may be exceeded. A derating of
the IGBT’s average gate power is required under these estimated exemplary conditions. Conditions
other than those specified may affect the reliability or lead to thermal breakdown of the gate
drivers. Please ask our support team for a specific estimation. As a rule, the case temperature of
any component of the gate driver should stay below 65°C for an ambient temperature of 25°C.
3) The total external gate resistance is the sum of the IGBT-internal chip resistances and the
externally used gate resistors. Note that the driver-internal minimum resistance is below 0.2Ω. Due
to the finite slew rate of the driver output voltage and to parasitic inductances in the gate control
loop, however, the resulting gate current may not approach the nominal maximum value of 16A.
4) Equivalent delay, rise or fall times are derived from comparisons with the results obtained when
modeling the driver as an ideal pulse-shaped voltage source with no delay and an infinite slew
rate.
5)
At the REF pin, a 1.5 kΩ resistor is connected to the positive voltage terminal Cs of the secondary-
side power supply in parallel with a nominal 150μA current source. The reference voltage may be
set via an external Zener diode or an external resistor connected to pin E. Furthermore, at pin ME
a 2.2 kΩ resistor is connected to Cs in parallel with a nominal 1.4mA current source.
6) Maximum continuous, or repeatedly applied DC voltage or peak value of the repeatedly applied AC
voltage between any primary-side pin and any secondary-side pin.
Caution for option C: operating voltages exceeding 600V may degrade the long-term
characteristics of the optocouplers, resulting in an increased delay or a reduced current capability
at pin SO.
7) The test voltage of 4000 Vac(rms)/50 Hz may be applied only one time and for one minute. It
should be noted that with this (strictly speaking obsolete) test method, some (minor) damage
