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ADG726BSUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
16-/32-Channel, 4 Ω, +1.8 V to +5.5 V and
±2.5 V Analog Multiplexers
Data Sheet
ADG726/ADG732
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
1.8 V to 5.5 V single-supply operation
±2.5 V dual-supply operation
On resistance: 4 Ω at 25°C (+5 V single supply/±2.5 V dual
supply)
0.5 Ω on-resistance flatness at 25°C (+5 V single supply/
±2.5 V dual supply)
Rail-to-rail operation
Transition times: 23 ns typical at 25°C
Single 32-to-1 channel multiplexer
Dual/differential 16-to-1 channel multiplexer
TTL-/CMOS-compatible inputs
48-lead TQFP or 48-lead, 7 mm × 7 mm LFCSP
APPLICATIONS
Optical applications
Data acquisition systems
Communication systems
Relay replacement
Audio and video switching
Battery-powered systems
Medical instrumentation
Automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAMS
S1A
S16A
DA
ADG726
EN
WR
A3
A2A1A0
S1B
S16B
DB
1-OF-16
DECODER
CSA
CSB
02765-001
Figure 1.
ADG732
EN
S1
S32
WR
CS
A4A3
A2A1A0
D
1-OF-32
DECODER
02765-002
EN
Figure 2.
GENERAL DESCRIPTION
The ADG726/ADG732 are monolithic, complementary metal
oxide semiconductor (CMOS) 32-channel and dual 16-channel
analog multiplexers. The ADG732 switches one of 32 inputs (S1
to S32) to a common output, D, as determined by the 5-bit binary
address lines A0, A1, A2, A3, and A4. The ADG726 switches one
of 16 inputs as determined by the 4-bit binary address lines A0,
A1, A2, and A3.
On-chip latches facilitate microprocessor interfacing. The ADG726
may also be configured for differential operation by tying
CSA
and
CSB
together. An
EN
input is used to enable or disable the
devices. When disabled, all channels are switched off.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high
switching speed, very low on resistance, and leakage currents.
They operate from a single supply of +1.8 V to +5.5 V and a
±2.5 V dual supply, making them ideally suited to a variety of
applications. On resistance is in the region of a few ohms and is
closely matched between switches and very flat over the full signal
range. These devices can operate equally well as either multiplexers
or demultiplexers and have an input signal range that extends to
the supplies. In the off condition, signal levels up to the supplies
are blocked. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
The ADG726/ADG732 are available in a 48-lead LFCSP or a
48-lead TQFP. For functionally equivalent devices with serial
interface, see the ADG725/ADG731.
PRODUCT HIGHLIGHTS
1. +1.8 V to +5.5 V single- or ±2.5 V dual-supply operation.
These devices are specified and guaranteed with +5 V ± 10%,
+3 V ± 10% single-supply, and ±2.5 V ± 10% dual-supply rails.
2. An on resistance of 4 Ω.
3. Guaranteed break-before-make switching action.
4. 48-lead LFCSP package or 48-lead TQFP package.
ADG726/ADG732 Data Sheet
Rev. B | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
+5 V Single Supply ....................................................................... 3
+3 V Single Supply ....................................................................... 5
±2.5 V Dual Supply ...................................................................... 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings ............................................................9
ESD Caution...................................................................................9
Pin Configurations and Function Description ........................... 10
48-Lead TQFP ............................................................................ 10
48-Lead LFCSP ........................................................................... 12
Typical Performance Characteristics ........................................... 15
Test Circuits ..................................................................................... 17
Terminology .................................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/15—Rev. A to Rev. B
Changes to Figure 4 and Table 6 ................................................... 10
Added Figure 5 and Table 7; Renumbered Sequentially ........... 11
Added Figure 6 and Table 8 ........................................................... 12
Changes to Figure 7, Table 9, and Table 10 ................................. 13
Changes to Table 11 ........................................................................ 14
2/15—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to Table 5 ............................................................................ 9
Added Table 6; Renumbered Sequentially .................................. 10
Added Table 7 .................................................................................. 11
Changes to Figure 5 ........................................................................ 11
Changes to Figure 8 to Figure 11 .................................................. 13
Changes to Figure 13 and Figure 15 to Figure 17 ....................... 14
Changes to Figure 25 to Figure 28 ................................................ 16
Changes to Figure 29 ...................................................................... 17
Moved Terminology Section ......................................................... 18
Changes to Terminology Section.................................................. 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
7/02—Revision 0: Initial Version
Data Sheet ADG726/ADG732
Rev. B | Page 3 of 21
SPECIFICATIONS
+5 V SINGLE SUPPLY
V
DD
= 5 V ± 10%, V
SS
= 0 V, G N D = 0 V, unless otherwise noted.
Table 1.
Parameter Symbol
ADG726/ADG732 ADG732
Unit Test Conditions/Comments +25°C
−40°C to
+85°C
−40°C to
+125°C
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance
R
ON
5
Ω typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA, see Figure 20
5.5 6 7 Ω max
On Resistance Match Between
Channels
ΔR
ON
0.3 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
0.8 1 Ω max
On Resistance Flatness R
FL AT (ON)
0.5 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
1 1.2 Ω max
LEAKAGE CURRENTS V
DD
= 5.5 V
Source Off Leakage
I
S
(Off )
nA typ
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V, see Figure 21
±0.25 ±1 ±2 nA max
Drain Off Leakage I
D
(Off ) ±0.05 nA typ V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V, see Figure 24
ADG726 ±0.5 ±2.5 nA max
ADG732 ±1 ±5 ±10 nA max
Channel On Leakage
I
D
, I
S
(On)
nA typ
V
D
= V
S
= 1 V, or 4.5 V, see Figure 25
ADG726 ±0.5 ±2.5 nA max
ADG732 ±1 ±5 ±10 nA max
DIGITAL INPUTS
Input High Voltage V
INH
2.4 2.4 V min
Input Low Voltage V
INL
0.8 0.8 V max
Input Current
Low or High I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.5 ±0.5 µA max
Digital Input Capacitance
C
IN
pF typ
DYNAMIC CHARACTERISTICS
1
Transition Time
t
TRANSITION
ns typ
R
L
= 300 Ω, C
L
= 35 pF, see Figure 27
34 40 48 ns max V
S1
= 3 V/0 V, V
S32
= 0 V/3 V
Break-Before-Make Time Delay t
D
18 ns typ R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 28
1 1 ns min
On Time (
CS
,
WR
) t
ON
(
CS
,
WR
) 18 ns typ R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 29
25 32 38.5 ns max
Off Time (
CS
,
WR
) t
OFF
(
CS
,
WR
) 17 ns typ R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 29
23 29 33 ns max
On Time (
EN
) t
ON
(
EN
) 24 ns typ R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 30
32 40 43 ns max
Off Time (
EN
) t
OFF
(
EN
) 16 ns typ R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 30
22 25 25 ns max
Charge Injection
Q
INJ
pC typ
V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 31
Off Isolation I
SO
−72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 22
Channel-to-Channel Crosstalk C
TK
−72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 23
−3 dB Bandwidth BW R
L
= 50 Ω, C
L
= 5 pF, see Figure 26
ADG726 34 MHz typ
ADG732 18 MHz typ
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADG726BSUZ

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Description:
Multiplexer Switch ICs 16:1 34MHz 4 Ohm Diff CMOS
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