ADG726/ADG732 Data Sheet
Rev. B | Page 12 of 21
48-LEAD LFCSP
S12A
S11A
S10A
S9A
S8
A
S7
A
S6
A
S5
A
S4A
S3A
S2A
S1A
S12B
S
1
1B
S10B
S9B
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S13A
S14A
S15A
S16A
NIC
DA
NIC
DB
S16B
S15B
S14B
S13B
PIN 1
INDICATOR
NOTES
1. NIC =
NOT INTERNALLY CONNECTED.
DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO GND.
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
ADG726
T
OP
VIEW
(Not to Scale)
02765-105
V
DD
V
SS
V
DD
A0
A1
A2
A3
CSA
CSB
WR
EN
GND
Figure 6. ADG726 Pin Configuration
Table 8. ADG726 Pin Function Description
Pin No. Mnemonic Description
1 to 12, 45 to 48 S16A to S1A Source Terminal. This pin may be an input or output.
13, 14 V
DD
Most Positive Power Supply Potential.
15 to 18 A0 to A3 Logic Control Inputs.
19
CSA
Chip Select Pin A.
CSA
is active low. If a differential output configuration is required, tie
CSA
and
CSB
together.
20
CSB
Chip Select Pin B.
CSB
is active low. If a differential output configuration is required, tie
CSB
and
CSA
together.
21
WR
Write pin. When
WR
is low, the logic control inputs (A0 to A3) control which state the switches are in. On
the rising edge of
WR
, the logic control input data is latched.
22
EN
Active Low, Digital Input. When this pin is high, the device is disabled and all switches are off. When this
pin is low, the Ax logic control inputs determine the on switches. The
EN
input signal is not latched by
WR
.
23 GND Ground (0 V) Reference.
24 V
SS
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect this pin
to GND.
25 to 40 S1B to S16B Source Terminal. This pin may be an input or output.
41 DB Drain Terminal. This pin may be an input or output.
42, 44 NIC Not Internally Connected. Do not connect to this pin.
43 DA Drain Terminal. This pin may be an input or output.
EPAD Exposed Pad. The exposed pad must be connected to GND.
