ADG726/ADG732 Data Sheet
Rev. B | Page 8 of 21
Parameter Symbol
ADG726/ADG732 ADG732
Unit Test Conditions/Comments +25°C
−40°C to
+85°C
−40°C to
+125°C
Off Switch Source Capacitance C
S
(Off) 13 pF typ
Off Switch Drain Capacitance C
D
(Off)
ADG726 137 pF typ f = 1 MHz
ADG732 275 pF typ f = 1 MHz
On Switch Drain, Source
Capacitance
C
D
, C
S
(On)
ADG726 150 pF typ f = 1 MHz
ADG732 300 pF typ f = 1 MHz
POWER REQUIREMENTS
Positive Supply Current I
DD
10 μA typ V
DD
= 2.75 V
20 20 μA max Digital inputs = 0 V or 2.75 V
Negative Supply Current I
SS
10 μA typ V
DD
= −2.75 V
20 20 μA max Digital inputs = 0 V or 2.75 V
1
Guaranteed by design; not subject to production test.
TIMING CHARACTERISTICS
Table 4.
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments
t
1
0 ns min
CS
to WR setup time
t
2
0 ns min
CS
to WR hold time
t
3
10 ns min
WR
pulse width
t
4
10 ns min
Time between WR
cycles
t
5
5 ns min Address, enable setup time
t
6
2 ns min Address, enable hold time
1
See Figure 3.
2
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
).
3
Guaranteed by design and characterization, not production tested.
t
1
t
2
t
3
t
4
t
5
t
6
CS
WR
A0, A1, A2, A3, (A4)
EN
02765-003
Figure 3. Timing Diagram
Figure 3 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore,
while
WR
is held low, the latches are transparent and the switches
respond to changing the address and enable the inputs.
Input data is latched on the rising edge of
WR
. The ADG726
has two
CS
inputs. This enables the device to be used either as a
dual 16-to-1 channel multiplexer or a differential 16-channel
multiplexer. If a differential output is required, tie
CSA
and
CSB
together.
