3©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017
879893 Datasheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1, 12, 16,
20, 29, 32,
37, 41, 45
GND Power Power supply ground.
2 QFB Output Clock feedback output. LVCMOS / LVTTL interface levels.
3 FB Input Pulldown Feedback control input. LVCMOS / LVTTL interface levels.
4 nMAN/A Input Pullup
Manual alarm input. Selects automatic switch mode or manual reference
clock. Clock failure detection, and nALARM_RST and CLK_IND output
flags are enabled. When LOW, IDCS is disabled. When HIGH, IDCS is
enabled. IDCS overrides REF_SEL on a clock failure. IDCS operation
requires nPLL_EN = 0. LVCMOS / LVTTL interface levels.
5, 13, 17,
21, 25, 36,
40, 44, 48
V
DD
Power Core supply pins.
6, 7 CLK0, CLK1 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
8V
DDA
Power Analog supply pin.
9 nALARM0 Output
When LOW, indicates clock failure on CLK0.
LVCMOS / LVTTL interface levels.
10 nALARM1 Output
When LOW, indicates clock failure on CLK1.
LVCMOS / LVTTL interface levels.
11 CLK_IND Output
Indicates currently selected input reference clock. When LOW, CLK0 is the
reference clock. When HIGH, CLK1 is the reference clock.
LVCMOS / LVTTL interface levels.
14, 15, 18,
19, 22, 23
QB5, QB4, QB3,
QB2, QB1, QB0
Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
26 nOE/MR Input Pulldown
Active High Master Reset. Active Low Output Enable. When logic LOW,
the internal dividers and the outputs are enabled. When logic HIGH, the
internal dividers are reset and the outputs are in a high-impedance state.
LVCMOS / LVTTL interface levels.
27, 28,
30, 31
FSEL3, FSEL2,
FSEL1, FSEL0
Input Pulldown
Clock frequency selection and configuration of clock divider modes.
LVCMOS / LVTTL interface levels.
33 nPLL_EN Input Pulldown
Selects PLL or static test mode. When LOW, PLL is enabled. When HIGH,
PLL is bypassed and IDCS is disabled. The VCO output is replaced by the
reference clock signal fREF. LVCMOS / LVTTL interface levels.
34 REF_SEL Input Pulldown
Selects the primary reference clock. When LOW, selects CLK0 as the
primary clock source. When HIGH, selects CLK1 as the primary clock
source. LVCMOS / LVTTL interface levels.
35 nALARM_RST Input Pullup
Resets the alarm flags and selected reference clock.
LVCMOS / LVTTL interface levels.
38, 39 42,
43, 46, 47
QA0, QA1, QA2,
QA3, QA4, QA5
Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
