13©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017
879893 Datasheet
Schematic Example
Figure 2 shows a schematic example of the 879893. In this
example, the CLK1 input is selected as primary. Both CLK0 and
CLK1 inputs are driven by LVCMOS drivers. For the LVCMOS
outputs, series termination is shown in this example. Additional
LVCMOS termination approached are shown in the LVCMOS
Termination Application Note. In this example, feedback trace is
assumed to be a long trace. The series termination near the QFB
pin is required. If the feedback trace is short, series termination is
not required. If this device is also used as a zero delay buffer, the
application note ZDB Delay Affected by Feedback Trace provides
additional information. For the power pins, it is recommended to
have at least one decoupling capacitor per power pin. The
decoupling capacitors should be physically located near the power
pins.
Figure 2. 879893 Schematic Example
C7
0.1u
Ro=14 Ohm
3.3V LVCMOS/LVTTL
Driver_LVCMOS
LVCMOS
VDD
VDDO
RD1
Not Install
CLK0
VDD=3.3V
VDD
C6
0.1u
LVCMOS
Zo = 50 Ohm
Zo = 50 Ohm
F_SEL3
F_SEL2
3.3V LVCMOS/LVTTL
LVCMOS/LVTTL
VDDO
VDD
R8 10
F_SEL1
nMAN/A
VDDO
nALARM1
LVCMOS/LVTTL
(U1,48)
To Logic
Input
pins
R2
1K
VDD
C31
0.1u
VDD
C40
10u
(U1,5)
C3
0.1u
(U1,13)
R25 36
VDD
VDD
F_SEL0
Status indicator
(U1,44)(U1,21)
R15 36
R1
1K
Set Logic
Input to
'0'
VDDA
R5
36
R4
36
(U1,17)
CLK_IND
nALARM0
QB5
QA5
Zo = 50 Ohm U1
ICS879893i
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
GND
QFB
FB
nMAN/A
VDD
CLK0
CLK1
VDD_PLL
nALARM0
nALARM1
CLK_IND
GND
VDD
QB5
QB4
GND
VDD
QB3
QB2
GND
VDD
QB1
QB0
GND
VDD
nALARM_RST
REF_SEL
nPLL_EN
GND
F_SEL0
F_SEL1
GND
F_SEL2
F_SEL3
nOE/MR
VDD
VDD
QA5
QA4
GND
VDD
QA3
QA2
GND
VDD
QA1
QA0
GND
VDD
Ro=14 Ohm
CLK1
LVCMOS/LVTTL
Hardwire Logic Input Pin Examples
VDDO=3.3V
C5
0.1u
C2
0.1u
LVCMOS
RU1
1K
(U1,25)
VDDO
Zo = 50 Ohm
C9
0.1u
Zo = 50 Ohm
C4
0.1u
Driver_LVCMOS
(U1,40)
RU2
Not Install
Set Logic
Input to
'1'
VDDO
C8
0.1u
C1
0.1u
To Logic
Input
pins
(U1,36)
RD2
1K
R16 36
14©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017
879893 Datasheet
Reliability Information
Table 6.
JA
vs. Air Flow Table for a 48 Lead LQFP
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for 879893 is: 4615
JA
vs. Air Flow
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
15©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017
879893 Datasheet
Package Outline and Package Dimensions
Package Outline - Y Suffix for 48 Lead LQFP
Table 7. Package Dimensions for 48 Lead LQFP
Reference Document: JEDEC Publication 95, MS-026
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N 48
A 1.60
A1 0.05 0.10 0.15
A2 1.35 1.4 1.45
b 0.17 0.22 0.27
c 0.09 0.15 0.20
D & E 9.00 Basic
D1 & E1 7.00 Basic
D2 & E2 5.50 Ref.
e 0.50 Basic
L 0.45 0.60 0.75
ccc 0.08

879893AYILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 12 LVCMOS OUT CLOCK GENERATOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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