7©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017
879893 Datasheet
AC Electrical Characteristics
Table 5A. AC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 2: These parameters are guaranteed by characterization. Not tested in production.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 7.5 200 MHz
f
REF
Input Frequency 15 100 MHz
BW PLL Closed Loop Bandwidth 0.8 to 4 MHz
t(Ø)
Propagation Delay, (Static Phase
Offset, CLKx to FB); NOTE 1, 2, 3
V
DD
= 3.3V±5%; FSEL = 111x -35 120 ps
V
DD
= 3.3V±5% -35 130 ps
tsk(o)
Output Skew;
NOTE 1, 2, 3, 4
within bank 50 ps
bank-to-bank 135 ps
any output to QFB 315 ps
t Rate of Period Change; NOTE 2
f
REF
= 62.5MHz, FSEL = 1000 160
ps/
cycle
FSEL = XXX0 100 280
ps/
cycle
FSEL = XXX1 200 425
ps/
cycle
tjit(cc) Cycle-to-Cycle Jitter; NOTE 2, 3
FSEL3 = 0 150 ps
FSEL3 = 1 190 ps
t
CYCLE
Output Clock Period Deviation when
switching from primary input to
secondary; NOTE 2
f
REF
= 62.5MHz, FSEL = 1000 -600 700 ps
-800 800 ps
tjit(per) Period Jitter; NOTE 2, 3
FSEL3 = 0 150 ps
FSEL3 = 1, measured on QBx 150 ps
tjit(Ø) I/O Phase Jitter, (1); NOTE 2, 3
FB = 4;
FSEL [0:2] = 100 or 111 (1)
25 ps
FB = 6;
FSEL [0:2] = 010 (1)
25 ps
FB = 8; FSEL [0:2] = 001, 011
or 110 (1)
35 ps
FB = 16;
FSEL [0:2] = 000 or 101 (1)
25 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 600 ps
t
PZL
, t
PZH
Output Enable Time; NOTE 2 10 ns
t
PLZ
, t
PHZ
Output Disable Time; NOTE 2 10 ns
t
L
PLL Lock Time; NOTE 2 10 ms
odc Output Duty Cycle 45 50 55 %
