NCP1256
www.onsemi.com
12
APPLICATION INFORMATION
NCP1256 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count and cost effectiveness are
key design parameters, particularly in low−cost ac−dc
adapters, open−frame power supplies etc. NCP1256 brings
all the necessary components normally needed in today
modern power supply designs, bringing several
enhancements such as a non−dissipative OPP, a brown−out
protection and two independent latch inputs for OVP/OTP
implementations. All these features are packed in a tiny
TSOP−6 package.
• Current−mode operation with internal slope
compensation: implementing peak current mode
control at a fixed 65−kHz or 100−kHz frequency, the
NCP1256 includes an internal slope compensation
signal whose level will cover most of offline design
cases. Additional ramp can be added via a simple
scheme around the feedback or current sense pin as
described below.
• Brown−out protection: a portion of the input mains
(or the rectified bulk rail) is brought to pin 3 via a
resistive network. When the voltage on this pin is too
low, the part stops pulsing. No re−start attempt is made
until the controller senses that the voltage is back
within its normal range. When the brown−out
comparator senses the voltage is acceptable, it sends a
general reset to the controller (latched states are
released) and authorizes re−start. Please note that a
re−start is always synchronized with a VCC
ON
transition event for a clean start−up sequence. If V
cc
is
naturally above VCC
ON
when the BO circuit recovers,
re−start is immediate.
• Internal OPP: the part internally buffers the brown out
voltage and transforms it into a current, sourced out of
the CS pin. By inserting a resistance between the sense
resistor and the CS pin, the designer has the ability to
build an offset and precisely adjust the OPP level he
needs. Please note that the OPP current starts from 0
when the BO voltage is 0.8 V, a low−line condition. It
helps pass maximum power at the lowest input voltage
despite a strong compensation at high line. OPP is also
disabled in frequency foldback mode for a better
light−load efficiency.
• Low startup current: reaching a low no−load standby
power always represents a difficult exercise when the
controller draws a significant amount of current during
start−up. Thanks to its proprietary architecture, the
NCP1256 is guaranteed to draw less than 10 mA
maximum (guaranteed at a 125−°C T
j
), easing the
design of low standby power adapters.
• EMI jittering: an internal low−frequency modulation
signal varies the pace at which the oscillator frequency
is modulated. This helps spreading out energy in
conducted noise analysis. To improve the EMI
signature at low power levels, the jittering is kept in
frequency foldback mode (light load conditions).
• Frequency foldback capability: a continuous flow of
pulses is not compatible with no−load/light−load
standby power requirements. To excel in this domain,
the controller observes the feedback pin and when it
reaches a level of 1.5 V, it starts reducing switching
frequency. When the feedback level reaches 1.2−V, the
frequency hits its lower stop at 26 kHz. When the
feedback pin goes further down and reaches 0.75 V, the
peak current setpoint is internally frozen at 31% of the
maximum limit. Below this point, if power continues to
drop, the feedback pins passes below 0.6 V and the
controller enters classical skip−cycle mode.
• Internal soft−start: a soft−start precludes the main
power switch from being stressed upon start up and it
reduces output voltage overshoots. In this controller,
the soft−start is internally fixed to 4 ms. Soft−start is
activated when a new startup sequence occurs or during
an auto−recovery hiccup.
• OVP inputs: the NCP1256 welcomes two inputs. One
is located in the brown out input whose upper dynamic
range is less than 3 V at a 375−V dc input. If an
external event lifts the BO pin above 4.5 V for four
consecutive clock cycles, the part permanently latches
off. Noise immunity is strengthened by reducing the
BO pin resistance when the voltage on the pin exceeds
3.3 V (beyond the OPP dynamic range). In the E
version, the clamp is removed and the fault is fully
auto−recovery for an efficient ac line OVP. The second
OVP input is placed in the current sense pin and is only
observed during the off−time duration. If during the off
time the current sense pin is lifted above 1.5 V typically
four consecutive clock cycles, the part latches off. By
connecting an NTC via a diode to the auxiliary
winding, a cheap and accurate OTP can be implemented.
Regardless of the trip mode (BO or CS), when latched,
V
cc
hiccups between both UVLO levels while all drive
pulses are off. Reset occurs when a) the BO voltage
drops below V
BO(off)
during a going−down V
cc
cycle or
b) V
cc
passes below the reset voltage VCC
reset
which is
V
CC(min)
−250 mV. When either event is detected, the
IC goes through a new fresh start−up sequence.
• V
cc
OVP: an OVP protects the circuit against V
cc
runaways. The fault must be present at least 20 ms to be
validated. This OVP is latched, except on E version
where it is auto−recovery.
• Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (the auxiliary winding
