NCP1256
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16
Please note that the IC will restart immediately if the BO
comparator sends the green light while V
cc
is above
VCC
ON
. In that case, as V
cc
is already high, there is no need
to go through a fresh start−up sequence and the part can
switch again.
Over Power Protection
Over Power Protection (OPP) is a known means to limit
the output power excursion at high mains. Several elements
such as propagation delays and operating mode explain why
a converter operated at high line delivers more power than
at low line. NCP1256 senses the input voltage via a resistive
network primarily used for brown−out protection. This line
image is transformed into a current information further
applied to the current sense pin (CS). A resistor placed in
series from the sense resistor to the CS pin will create an
offset voltage proportional to the input voltage variation. An
added current sink will ensure a 0 OPP current at low line,
leaving the converter power capability intact in the lowest
operating voltage. Figure 37 presents the internal simplified
architecture of this OPP circuitry.
CS
BO
vdd
OPPGM
IOPPLL
ICSO
Rupper
Rlower
ROPP
Rsense
To CS
comparator
VFB > VfoldF Iopp3 = I1
VFB < VoppF Iopp3 = 0
I2=0
I1=I2
VFB
Iopp3
I1
I2
C1
Vbulk
VfoldF
V(FB)
offset
Figure 37. Over Power Protection is provided via the bulk voltage image present on Brown−Out pin
We assume the brown−out network is tweaked so that a
80−V rms input voltage brings 0.8 V on the BO pin. This is
the voltage at which the adapter will start working. The
voltage will be transformed into a current by the OPPGM
block. Its transconductance is 115 mS, leading to a generated
current of 92 mA at a 0.8−V bias. However, there is an
internal fixed current sink IOPPLL calibrated so that the net
current flowing into R
OPP
is 0 at this low−voltage input. It
ensures an almost non−compensated converter at low line.
Now, assume a 265−V input voltage, the BO level will be
2.65 V and will generate an offset current of 185 mA as stated
in the specs. In our design, as an example, say we need to
reduce the maximum peak current setpoint by 250 mV to
reduce the maximum power at the 265−V input. In that case,
we will need to generate a 250−mV offset across R
OPP
. With
a 185−mA current, R
OPP
should be equal to 230 m / 185 u =
1.35 kW. A small 100−220 pF capacitor closely connected
between the CS and GND pins will form an effective noise
filter and will nicely improve the converter immunity to
noise. Please note that the OPP current is clamped for a BO
pin voltage greater than 2.65 V. Should you lift the pin above
this voltage, there will be no increase of the OPP current and
the current absorbed by the pin will increase as you approach
the OVP level.
The offset voltage can affect the standby power
performance by reducing the peak current setpoint in
light−load conditions. For this reason, it is desirable to
smoothly cancel its action as soon as frequency folback
occurs. A typical curve variation is shown in Figure 38. At
low power, below the frequency folback starting point,
100% of the OPP current is internally absorbed and no offset
is created through the CS pin. When feedback increases
again and reaches the frequency foldback point, as the
frequency goes up, OPP starts to build up and reaches its full
value at V
foldF
+ 0.7 V.
NCP1256
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17
t
V
V
FB
max
V
foldF
+0.7 V
t
%
OPP
current
100
0
F
sw
decreases
F
sw
increases
Figure 38. The OPP current is applied when the
feedback voltage exceeds the folback point.
It is 0 below it
Latch on Brown−Out Input
It is possible to latch the controller if an external event
brings the BO input above V
latch1
for four consecutive clock
cycles. The simplified internal circuitry appear in Figure 39
where OVP is triggered from the secondary side via a
dedicated optocoupler. To improve the controller noise
immunity, a circuit made of an active Zener diode and a
series resistor reduce the pin impedance as the voltage starts
to increase above 3.3 V. More current is thus needed to
actually trigger the internal latch. The example shows how
an external event (an OVP in the secondary side for instance)
can trip the latch. R
5
ensures enough bias circulates in the
optocoupler while D
2
isolates the circuit from the high−
impedance BO bridge. As the voltage on the BO pin starts
increasing beyond 3.3 V, more current is drawn on the
optocoupler (R
dBO
is 1 kW typically) and when the BO voltage
touches the 4.5−V trip point, the circuit latches off after 4
consecutive clock cycles. If the OVP assertion disappears
before the counter counts to 4, a counter reset occurs.
A primary−side version of the above circuit can be
implemented with the help of a single Zener diode as shown
in Figure 40. The Zener will lift the BO pin when the
feedback loop is lost and will latch the part immediately.
In latch−off mode, the V
cc
keeps hiccupping for ever
between VCC
ON
and VCC
(min)
while the drive output is cut.
To reset the latch, either cycle the input voltage so that the
BO pin passes below V
BOoff
or unplug the adapter until the
controller V
cc
goes below VCC
reset
. In either case, the
controller will resume via a fresh start−up sequence.
With the E version, the current clamp is removed and the
fault is auto−recovery for ac line OVP implementation. You
can design in two different ways:
1. You select the ac line OVP and then have a
corresponding BO on: assume you design the
sensing network to have 4.5 V for 320 Vrms, then,
the BO on is 320 x 0.8/4.5 = 57 Vrms.
2. You select the BO on voltage and have a
corresponding ac line OVP: assume a turn on
voltage of 60 Vrms, then the ac line OVP voltage
is set to 60 x 4.5/0.8 = 337 Vrms.
Power on
reset
1−us time
constant
Vlatch1
S
R
Q
Q
Up counter
4
RST
OVP
gone?
BO
RdBO
DZBO
BO
reset
latch
Vbulk
D2
R5
R1
R2
Vcc
Figure 39. The circuit can easily be latched via a dedicated optocoupler observing the secondary side voltage
NCP1256
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18
Q1
Rsense
R2
1k
DRV
CS
Vcc
Vcc
BO
R3
C3
R4
Bulk
D3
1N4148
R5
1k
D4
Figure 40. A simple Zener diode (D
4
) can also be wired on the BO pin, latching off the part in case V
cc
runs
away (if the secondary−side LED is shorted for instance). Make sure R
3
, R
4
, R
5
D
3
, D
4
and C
3
are closely
located to the controller
Auto−Recovery Short−Circuit Protection
In case of output short−circuit or if the power supply
experiences a severe overloading situation, an internal error
flag is raised and starts a countdown timer. The flag is raised
at the first maximum peak current event. If the flag is
asserted longer than its programmed value (70 ms typical),
the driving pulses are stopped and V
cc
falls down as the
auxiliary pulses are missing. V
cc
fall out is ensured by the
part natural consumption in this mode which is around
400 mA. To ensure V
cc
hiccup and thus autorecovery, the
start−up current must always be less than these 400 mA
otherwise recovery will be lost. Timer reset occurs when 8
successive resets coming from the feedback back into
regulation. When the V
cc
level crosses VCC
(min)
, the
controller consumption is down to a few mA and the V
cc
slowly builds up again thanks to the resistive starting
network. When V
cc
reaches VCC
ON
, the controller
purposely ignores the re−start and waits for another V
cc
cycle: this is the so−called double hiccup. By lowering the
duty ratio in fault condition, it naturally reduces the average
input power and the rms current in the output cable.
Illustration of such principle appears in Figure 41. Please
note that soft−start is activated upon re−start attempt.
8.8 V
18 V
()
cc
Vt
()
DRV
Vt
No pulse
area
Figure 41. An auto−recovery hiccup mode is entered in case a faulty
event longer than 70 ms is acknowledged by the controller

NCP1256BSN100T1G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers NCP1256B 100KHZ
Lifecycle:
New from this manufacturer.
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