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9FG1904BK-1LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
13
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
1255B—08/03/07
9FG1904-1 SMBus Address Mapping
when using CK410/CK410B, 9FG1200, and
9DB401/801
SMB Adr: DC
9DB401/801
(DB400/800)
SMB Adr: D2
954101
932S401
(CK410/410B)
PLL BYPASS MODE
SMB_A2_PLLBYP# = 0
P
L
L
Z
D
B
M
O
D
E
S
M
B
_
A
2
_
P
L
L
B
Y
P
#
=
1
SMB_A(2:0) = 100
SMB Adr: D8
SMB_A(2:0) = 101
SMB Adr: DA
SMB_A(2:0) = 110
SMB Adr: DC
SMB_A(2:0) = 111
SMB Adr: DE
SMB_A(2:0) = 000
SMB Adr: D0
9FG1904-1
(DB1900GS)
SMB_A(2:0) = 001
SMB Adr: D2
SMB_A(2:0) = 010
SMB Adr: D4
SMB_A(2:0) = 011
SMB Adr: D6
SMB_A(2:0) = 100
SMB Adr: D8
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 101
SMB Adr: DA
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 110
SMB Adr: DC
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 111
SMB Adr: DE
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 000
SMB Adr: D0
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 001
SMB Adr: D2
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 010
SMB Adr: D4
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 011
SMB Adr: D6
9FG1200-1
(DB1200GS)
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR
`
9FG1904-1
(DB1900GS)
9FG1904-1
(DB1900GS)
9FG1904-1
(DB1900GS)
9FG1904-1
(DB1900GS)
9FG1904-1
(DB1900GS)
9FG1904-1
(DB1900GS)
9FG1904-1
(DB1900GS)
14
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
1255B—08/03/07
General SMBus serial interface information for the ICS9FG1904B-1
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address *D0
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address *D0
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address *D1
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address *D0
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address *D1
(H)
Index Block Read Operation
Slave Address *D0
(H)
Beginning Byte = N
ACK
ACK
* The SMBus Address of this device is programmable.
See the preceding page for details on how to set the
SMBus address.
15
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
1255B—08/03/07
SMBusTable: Gear Ratio Select Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7
RW Gear Ratio 1:1
1
Bit 6
RW Gear Ratio 1:1
1
Bit 5
RW 1
Bit 4
RW Latch
Bit 3
RW 1
Bit 2
RW 0
Bit 1
RW 1
Bit 0
RW 1
SMBusTable: Output Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7
DIF_7 Output Control RW Hi-Z Enable 1
Bit 6
DIF_6 Output Control RW Hi-Z Enable 1
Bit 5
DIF_5 Output Control RW Hi-Z Enable 1
Bit 4
DIF_4 Output Control RW Hi-Z Enable 1
Bit 3
DIF_3 Output Control RW Hi-Z Enable 1
Bit 2
DIF_2 Output Control RW Hi-Z Enable 1
Bit 1
DIF_1 Output Control RW Hi-Z Enable 1
Bit 0
DIF_0 Output Control RW Hi-Z Enable 1
SMBusTable: Output and PLL BW Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7
RW High BW Low BW
1
Bit 6
RW Bypass PLL
1
Bit 5
DIF_13 Output Control RW Hi-Z Enable 1
Bit 4
DIF_12 Output Control RW Hi-Z Enable 1
Bit 3
DIF_11 Output Control RW Hi-Z Enable 1
Bit 2
DIF_10 Output Control RW Hi-Z Enable 1
Bit 1
DIF_9 Output Control RW Hi-Z Enable 1
Bit 0
DIF_8 Output Control RW Hi-Z Enable 1
Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW
Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7
R X
Bit 6
R X
Bit 5
R X
Bit 4
R X
Bit 3
R X
Bit 2
R X
Bit 1
R X
Bit 0
R X
72
Readback
Readback - OE5# Input
Readback - OE6# Input
Readback
Readback
Readback - OE8# Input
Readback
Readback
Readback - OE7# Input
Readback - OE9# Input
see note PLL_BW# adjust
see note BYPASS# test mode / PLL
8
B
y
te 1
-
-
-
-
B
y
te 0
DIF(14:0)
DIF(18:15)
Gear Ratio FS4 (Inverse of FS_A_410 input!)
-
-
Group of 15 gear ratio enable
Group of 4 gear ratio enable
Reserved
B
y
te 3
ReadbackReadback - OE_01234# Input
Readback - SMB_A2_PLLBYP# In Readback
Readback - HIGH_BW# In Readback
B
y
te 2
Gear Ratio FS3
Gear Ratio FS2
Gear Ratio FS1
See ICS9FG1904-1
Programmable Gear
Ratios Table
Gear Ratio FS0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

9FG1904BK-1LF

Mfr. #:
Buy 9FG1904BK-1LF
Manufacturer:
IDT
Description:
Clock Buffer PCIE BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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