MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________ 19
Table 10. Transfer-Function Register Mapping—Gain-Cal Mode (M1 = 1, M0 = 0)
X = Don’t Care.
First Bit (Data MSB)
RESERVED BITS
CHANNEL ID TAG
D1
‘0’
D0 ‘0’
‘0’ CID0
DATA BITS
CID2
CID1
D9 D5D8 D7 D6 D2
DATA BITS
D4 D3
(Data LSB) (LSB)
D17 D13D16 D15 D14 D10
DATA BITS
D12 D11
0
DIFF
0
A1
0 0 10
0 1
0 1 20
2
1
0
0
0 X
0 X 11
0 X
0 X 21
2
1
1
1
1 0
1 0 2
SCAN
0
1 1
TRANSFER
FUNCTION REG.
1 X
1 X
3
1
0
0
0 X
0 X 31
0 X
1 X 11
3
3
1
1
0
A0
1
0
1
X
X
X
X
0
1
0
3
X
X
X
X
CALGAIN+–CALGAIN-
CALGAIN+–CALGAIN-
CALGAIN+–CALGAIN-
CALGAIN+–CALGAIN-
AIN2–AIN6
AIN4–AIN6
AIN3–AIN6
AIN1–AIN6
CALGAIN+–CALGAIN-
CHANNEL
1
CALGAIN+–CALGAIN-
CALGAIN+–CALGAIN-
CALOFF+–CALOFF-
AIN1–AIN2
CALGAIN+–CALGAIN-
AIN5–AIN6
1 X
1 X 31
3
2
1
1 X
X
X
X
AIN5–AIN6
CALGAIN+–CALGAIN-
CALOFF+–CALOFF-
AIN3–AIN4
1 1 Do not use0 1
1 1 Do not use1 1
Data Register (Read-Only)
The data register is a 24-bit, read-only register. Any
attempt to write data to this location will have no effect.
If a write operation is attempted, 8 bits of data must be
clocked into the part before it will return to its normal
idle mode, expecting a write to the communications
register.
Data is output MSB first, followed by three reserved 0
bits and a 3-bit channel ID tag indicating the channel
from which the data originated.
D17–D0: The conversion result. D17 is the MSB. The
result is in offset binary format. 00 0000 0000 0000
0000 represents the minimum value and 11 1111 1111
1111 1111 represents the maximum value. Inputs
exceeding the available input range are limited to the
corresponding minimum or maximum output values.
0: These reserved bits will always be 0.
CID2–0: Channel ID tag (Table 11).
Data Register (Read-Only) Bits
MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
20 ______________________________________________________________________________________
Table 11. Channel ID Tag Codes
Switching Network
A switching network provides selection between three
fully differential input channels or five pseudo-differen-
tial channels, using AIN6 as a shared common. The
switching network provides two additional fully differen-
tial input channels intended for system calibration,
which may be used as extra fully differential signal
channels. Table 12 shows the channel configurations
available for both operating modes.
Scanning (SCAN-mode)
To sample and convert the available input channels
sequentially, set the SCAN control bit in the global
setup register. The sequence is determined by DIFF
(fully differential or pseudo-differential) and by the
mode control bits M1 and M0 (Tables 8, 9, 10). With
SCAN set, the part automatically sequences through
each available channel, transmitting a single conver-
sion result before proceeding to the next channel. The
MAX1400 automatically allows sufficient time for each
conversion to fully settle, to ensure optimum resolution
before asserting the data-ready signal and moving to
the next available channel. The scan rate is, therefore,
dependent on the clock bit (CLK), the filter control bits
(FS1, FS0), and the modulator frequency selection bits
(MF1, MF0).
Burnout Currents
The input circuitry also provides two “burnout” currents.
These small currents may be used to test the integrity
of the selected transducer. They can be selectively
enabled or disabled by the BOUT bit in the global
setup register.
CHANNELCID2
1
1
AIN1–AIN2
AIN5–AIN6
1 Calibration11
01
1 AIN3–AIN410
00
0
0
AIN1–AIN6
AIN3–AIN6
0 AIN4–AIN611
01
0 AIN2–AIN610
CID0
0
CID1
0
Table 12. Input Channel Configuration in Fully and Pseudo-Differential Modes
(SCAN = 0)
X = Don’t Care.
* This combination is available only in pseudo-differential mode when using the internal scanning logic
** These combinations are only available in the calibration modes.
0
M0
0
DIFF
0 0 AIN20
0 0
0 0 AIN40
AIN3
AIN1
0
0
0 1
0 1 AIN30
0 1
1 X CALOFF+**0
AIN5
AIN1
0
0
0 X
1 X CALOFF+**
M1
0
0 X
HIGH INPUT
CALGAIN+**
AIN5*
1
0
0 X CALGAIN+**1
0
A1
0
1
1
0
0
1
X
X
X
X
X
MODE
Pseudo-
Differential
Fully
Differential
0
A0
1
0
1
0
1
0
X
X
X
X
X
AIN6
AIN6
AIN6
AIN6
AIN4
CALOFF-**
AIN6
AIN2
CALOFF-**
LOW INPUT
CALGAIN-**
AIN6*
CALGAIN-**
MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________ 21
External Access to Mux Outputs
The MAX1400 provides access to the switching-net-
work output and the modulator input with the MUXOUT
and ADCIN pins. This allows the user to share a single
high-performance amplifier for additional signal condi-
tioning of all input channels.
Dynamic Input Impedance at the
Channel Selection Network
When used in unbuffered mode (BUFF = 0), the analog
inputs present a dynamic load to the driving circuitry.
The size of the sampling capacitor and the input sam-
pling frequency (Figure 5) determine the dynamic load
seen by the driving circuitry. The MAX1400 samples at a
constant rate for all gain settings. This provides a maxi-
mum time for the input to settle at a given data rate. The
dynamic load presented by the inputs varies with the
gain setting. For gains of +2V/V, +4V/V, and +8V/V, the
input sampling capacitor increases with the chosen
gain. Gains of +16V/V, +32V/V, +64V/V, and +128V/V
present the same input load as the x8 gain setting.
When designing with the MAX1400, as with any other
switched-capacitor ADC input, consider the advan-
tages and disadvantages of series input resistance. A
series resistor reduces the transient-current impulse to
the external driving amplifier. This improves the amplifi-
er phase margin and reduces the possibility of ringing.
The resistor spreads the transient-load current from the
sampler over time due to the RC time constant of the
circuit. However, an improperly chosen series resis-
tance can hinder performance in fast 16-bit converters.
The settling time of the RC network can limit the speed
at which the converter can operate properly, or reduce
the settling accuracy of the sampler. In practice, this
means ensuring that the RC time constant—resulting
from the product of the driving source impedance and
the capacitance presented by both the MAX1400’s
input and any external capacitances—is sufficiently
small to allow settling to the desired accuracy. Tables
13a–13d summarize the maximum allowable series
resistance vs. external capacitance for each MAX1400
gain setting in order to ensure 16-bit performance in
unbuffered mode.
R
EXT
C
EXT
R
MUX
C
PIN
MUXOUT ADCIN
R
SW
C
ST
C
PIN
C
SAMPLE
C
C
Figure 5. Analog Input, Unbuffered Mode (BUFF = 0)
Table 13a. R
EXT
, C
EXT
Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode—1x Modulator Sampling Frequency (MF1, MF0 = 00); X2CLK = 0; f
CLKIN
= 2.4576MHz
Table 13b. R
EXT
, C
EXT
Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode—2x Modulator Sampling Frequency (MF1, MF0 = 00); X2CLK = 0; f
CLKIN
= 2.4576MHz
38 18
38 18 12.52
29 16
20 12.7 9.3
8, 16, 32,
64, 128
11.1
12.5
4
1
C
EXT
= 0pF C
EXT
= 50pF C
EXT
= 100pF
3.8 2.1
3.8 2.1 0.57
3.5 2.0
3.2 1.8 0.48
0.53
PGA GAIN
0.57
C
EXT
= 500pF C
EXT
= 1000pF C
EXT
= 5000pF
EXTERNAL RESISTANCE R
EXT
(k)
19 9.2
19 9.2 6.22
14 8.0
10 6.3 4.6
8, 16, 32,
64, 128
5.5
6.2
4
1
C
EXT
= 0pF C
EXT
= 50pF C
EXT
= 100pF
1.9 1.0
1.9 1.0 0.28
1.7 1.0
1.6 0.92 0.24
0.26
PGA GAIN
0.28
C
EXT
= 500pF C
EXT
= 1000pF C
EXT
= 5000pF
EXTERNAL RESISTANCE R
EXT
(k)

MAX1400CAI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 18-Bit 5Ch 4.8ksps 2.5V Precision ADC
Lifecycle:
New from this manufacturer.
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