Operation M41T11
10/30 Doc ID 6103 Rev 10
Figure 6. Acknowledgement sequence
Figure 7. Bus timing requirements sequence
1. P = STOP and S = START
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCLK FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
12 89
MSB LSB
AI00589
SDA
P
tSU:STOtSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STAtBUF
SP
M41T11 Operation
Doc ID 6103 Rev 10 11/30
2.2 Read mode
In this mode, the master reads the M41T11 slave after setting the slave address (see
Figure 8). Following the write mode control bit (R/W
= 0) and the acknowledge bit, the word
address A
n
is written to the on-chip address pointer. Next the START condition and slave
address are repeated, followed by the READ mode control bit (R/W
= 1). At this point, the
master transmitter becomes the master receiver. The data byte which was addressed will be
transmitted and the master receiver will send an acknowledge bit to the slave transmitter
(see Figure 9). The address pointer is only incremented on reception of an acknowledge bit.
The M41T11 slave transmitter will now place the data byte at address A
n
+ 1 on the bus. The
master receiver reads and acknowledges the new byte and the address pointer is
incremented to A
n
+ 2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T11
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 10 on page 12).
Table 2. AC characteristics
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= –40 to 85°C; V
CC
= 2.0 to 5.5 V (except where noted).
Min Max Unit
f
SCL
SCL clock frequency 0 100 kHz
t
LOW
Clock low period 4.7 µs
t
HIGH
Clock high period 4 µs
t
R
SDA and SCL rise time 1 µs
t
F
SDA and SCL fall time 300 ns
t
HD:STA
START condition hold time
(after this period the first clock pulse is generated)
s
t
SU:STA
START condition setup time
(only relevant for a repeated start condition)
4.7 µs
t
SU:DAT
Data setup time 250 ns
t
HD:DAT
(2)
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling
edge of SCL.
Data hold time 0 µs
t
SU:STO
STOP condition setup time 4.7 µs
t
BUF
Time the bus must be free before a new transmission can start 4.7 µs
Operation M41T11
12/30 Doc ID 6103 Rev 10
Figure 8. Slave address location
Figure 9. Read mode sequence
Figure 10. Alternate read mode sequence
AI00602
R/W
SLAVE ADDRESS
START A
0100011
MSB
LSB
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS

M41T11M6F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Real Time Clock Serial 512 (64x8)
Lifecycle:
New from this manufacturer.
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