M41T11M6F Datasheet M41T11M6F, M41T11MH6F, M41T11M6E | P13-P15

M41T11 Operation

Doc ID 6103 Rev 10 13/30

2.3 Write mode

In this mode the master transmitter transmits to the M41T11 slave receiver. Bus protocol is

shown in Figure 11. Following the START condition and slave address, a logic '0' (R/W

= 0)

is placed on the bus and indicates to the addressed device that word address An will follow

and is to be written to the on-chip address pointer. The data word to be written to the

memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41T11

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address and again after it has received the word address and each data byte.

2.4 Data retention mode

With valid V

applied, the M41T11 can be accessed as described above with read or write

cycles. Should the supply voltage decay, the M41T11 will automatically deselect, write

protecting itself when V

falls (see Figure 15).

Figure 11. Write mode sequence

AI00591

BUS ACTIVITY:

ACK

STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

Clock operation M41T11

14/30 Doc ID 6103 Rev 10

3 Clock operation

The eight byte clock register (see Ta ble 3) is used to both set the clock and to read the date

and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are

contained within the first three registers. Bits D6 and D7 of clock register 2 (hours register)

contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1'

will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century

(depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2

of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of

month), month and years. The final register is the control register (this is described in the

clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a

'1' will cause the oscillator to stop. If the device is expected to spend a significant amount of

time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'

the oscillator restarts within one second.

Note: In order to guarantee oscillator startup after the initial power-up, set the ST bit to a '1,' then

reset this bit to a '0.' This sequence enables a “kick start” circuit which aids the oscillator

startup during worst case conditions of voltage and temperature.

The seven clock registers may be read one byte at a time, or in a sequential block. The

control register (address location 7) may be accessed independently. Provision has been

made to assure that a clock update does not occur while any of the seven clock addresses

are being read. If a clock address is being read, an update of the clock registers will be

delayed by 250 ms to allow the read to be completed before the update occurs. This will

prevent a transition of data during the read.

Note: This 250 ms delay affects only the clock register update and does not alter the actual clock

time.

M41T11 Clock operation

Doc ID 6103 Rev 10 15/30

3.1 Clock calibration

The M41T11 is driven by a quartz controlled oscillator with a nominal frequency of

32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator

frequency error at 25°C, which equates to about ±1.53 minutes per month. With the

calibration bits properly set, the accuracy of each M41T11 improves to better than ±2 ppm

at 25°C.

The oscillation rate of any crystal changes with temperature (see Figure 12 on page 17).

Most clock chips compensate for crystal frequency and temperature shift error with

cumbersome trim capacitors. The M41T11 design, however, employs periodic counter

correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure 13 on page 17. The number of times pulses

are blanked (subtracted, negative calibration) or split (added, positive calibration) depends

upon the value loaded into the five-bit calibration byte found in the control register. Adding

counts speeds the clock up, subtracting counts slows the clock down.

The calibration byte occupies the five lower order bits (D4-D0) in the control register (addr

7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is a

sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs

within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one

second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of

Table 3. Register map

(1)

1. Keys:

S = SIGN bit

FT = FREQUENCY TEST bit

ST = STOP bit

OUT = Output level

X = Don’t care

CEB = Century enable bit

CB = Century bit

Address

Data

Function/range

BCD format

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 seconds Seconds Seconds 00-59

1 X 10 minutes Minutes Minutes 00-59

2CEB

(2)

2. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the

initial value set). When CEB is set to '0', CB will not toggle.When CEB is set to '1', CB will toggle from '0' to

'1' or from '1' to '0' every 100 years (dependent upon the initial value set). When CEB is set to '0', CB will

not toggle.

CB 10 hours Hours Century/hours 0-1/00-23

3 X X X X X Day Day 01-07

4 X X 10 date Date Date 01-31

5 X X X 10 M. Month Month 01-12

6 10 years Years Year 00-99

7 OUT FT S Calibration Control

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

M41T11M6F

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