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ATF1502ASL-25AI44

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1
Features
• High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
–44Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell
– D/T Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features
• Automatic10µAStandbyfor“L”Version
• Pin-controlled 1 mA Standby Mode
• Programmable Pin-keeper Inputs and I/Os
• Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-lead PLCC and TQFP
• Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• Security Fuse Feature
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• D Latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
(“L” versions)
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• V
CC
Power-up Reset Option
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Input Transition Detection
– Power-down (“L” versions)
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
High-
performance
EEPROM CPLD
ATF1502AS
ATF1502ASL
Rev. 0995J–PLD–09/02
2
ATF1502AS(L)
0995J–PLD–09/02
44-lead TQFP
Top View
44-lead PLCC
Top View
Description The ATF1502AS is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells
and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic
PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count and
the odds of successful pin-locked design modifications.
The ATF1502AS has up to 32 bi-directional I/O pins and four dedicated input pins, depending
on the type of device package selected. Each dedicated pin can also serve as a global control
signal, register clock, register reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
GND
GCLK3/I/O
I/O
3
ATF1502AS(L)
0995J–PLD–09/02
Block Diagram
Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input
and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40
individual signals from the global bus. Each macrocell also generates a foldback logic term
that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast,
efficient generation of complex logic functions. The ATF1502AS contains four such logic
chains, each capable of creating sum term logic with a fan-in of up to 40 product terms.
The ATF1502AS macrocell, shown in Figure 1, is flexible enough to support highly complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
Unused product terms are automatically disabled by the compiler to decrease power con-
sumption. A security fuse, when programmed, protects the contents of the ATF1502AS. Two
bytes (16 bits) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of
the state of the security fuse.
The ATF1502AS device is an in-system programmable (ISP) device. It uses the industry stan-
dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-
scan Description Language (BSDL). ISP allows the device to be programmed without remov-
ing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also
allows design modifications to be made in the field via software.
B
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ATF1502ASL-25AI44

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Description:
IC CPLD 32MC 25NS 44TQFP
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