10
ATF1502AS(L)
0995J–PLD–09/02
PCI Compliance The ATF1502AS also supports the growing need in the industry to support the new Peripheral
Component Interconnect (PCI) interface standard in PCI-based designs and specifications.
The PCI interface calls for high current drivers, which are much larger than the traditional TTL
drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required
by the PCI interface. The ATF1502AS allows this without contributing to system noise while
delivering low output to output skew. Having a programmable high drive option is also possible
without increasing output delay or pin capacitance. The PCI electrical characteristics appear
on the next page.
PCI Voltage-to-
current Curves
for +5V
Signaling in
Pull-up Mode
PCI Voltage-to-
current Curves
for +5V
Signaling in
Pull-down Mode
2.4
VCC
1.4
-2
-44
-178
Current (mA)
AC drive
point
DC
drive point
Voltage
Pull Up
Test Point
2.2
VCC
0.55
3,6
95
380
Current (mA)
AC drive
point
DC
drive point
Voltage
Pull Down
Test Point
11
ATF1502AS(L)
0995J–PLD–09/02
Note: 1. Leakage current is with pin-keeper off.
Notes: 1. Equation A: I
OH
=11.9(V
OUT
- 5.25) * (V
OUT
+ 2.45) for V
CC
>V
OUT
>3.1V.
2. Equation B: I
OL
= 78.5 * V
OUT
*(4.4-V
OUT
)for0V<V
OUT
< 0.71V.
PCI DC Characteristics (Preliminary)
Symbol Parameter Conditions Min Max Units
V
CC
Supply Voltage 4.75 5.25 V
V
IH
Input High Voltage 2.0 V
CC
+0.5 V
V
IL
Input Low Voltage -0.5 0.8 V
I
IH
Input High Leakage Current
(1)
V
IN
=2.7V 70 µA
I
IL
Input Low Leakage Current
(1)
V
IN
= 0.5V -70 µA
V
OH
Output High Voltage I
OUT
=-2mA 2.4 V
V
OL
Output Low Voltage I
OUT
=3mA,6mA 0.55 V
C
IN
Input Pin Capacitance 10 pF
C
CLK
CLK Pin Capacitance 12 pF
C
IDSEL
IDSEL Pin Capacitance 8 pF
L
PIN
Pin Inductance 20 nH
PCI AC Characteristics (Preliminary)
Symbol Parameter Conditions Min Max Units
I
OH(AC)
Switching
Current High
(Test High)
0<V
OUT
1.4 -44 mA
1.4 < V
OUT
<2.4 -44+(V
OUT
-1.4)
/0.024
mA
3.1 < V
OUT
<V
CC
Equation A mA
V
OUT
= 3.1V -142 µA
I
OL(AC)
Switching
Current Low
(Test Point)
V
OUT
>2.2V 95 mA
2.2 > V
OUT
>0 V
OUT
/0.023 mA
0.1 > V
OUT
> 0 Equation B mA
V
OUT
=0.71 206 mA
I
CL
Low Clamp Current -5 < V
IN
-1 -25 + (V
IN
+1)
/0.015
mA
SLEW
R
Output Rise Slew Rate 0.4V to 2.4V load 1 5 V/ns
SLEW
F
Output Fall Slew Rate 2.4V to 0.4V load 1 5 V/ns
12
ATF1502AS(L)
0995J–PLD–09/02
Power-down
Mode
The ATF1502AS includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply
current is reduced to less than 5 mA. During power-down, all output data and internal logic
states are latched and held. Therefore, all registered and combinatorial output data remain
valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold
latches remain active to ensure that pins do not float to indeterminate levels, further reducing
system power. The power-down pin feature is enabled in the logic design file. Designs using
the power-down pin may not use the PD pin logic array input. However, all other PD pin mac-
rocell resources may still be used, including the buried feedback and foldback product term
array inputs.
Notes: 1. For slow slew outputs, add t
SSO
.
2. Pin or product term.
Power-down AC Characteristics
(1)(2)
Symbol Parameter
-7 -10 -15 -25
UnitsMin Max Min Max Min Max Min Max
t
IVDH
Valid I, I/O before PD High 7 10 15 25 ns
t
GVDH
Valid OE
(2)
before PD High 7 10 15 25 ns
t
CVDH
Valid Clock
(2)
before PD High 7 10 15 25 ns
t
DHIX
I, I/O Don’t Care after PD High 12 15 25 35 ns
t
DHGX
OE
(2)
Don’t Care after PD High 12 15 25 35 ns
t
DHCX
Clock
(2)
Don’t Care after PD High 12 15 25 35 ns
t
DLIV
PD Low to Valid I, I/O 1 1 1 1 µs
t
DLGV
PD Low to Valid OE (Pin or Term) 1 1 1 1 µs
t
DLCV
PD Low to Valid Clock (Pin or Term) 1 1 1 1 µs
t
DLOV
PD Low to Valid Output 1 1 1 1 µs
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
CC
+0.75VDC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)

ATF1502ASL-25AI44

Mfr. #:
Manufacturer:
Description:
IC CPLD 32MC 25NS 44TQFP
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New from this manufacturer.
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