©2011 Silicon Storage Technology, Inc. DS25045A 09/11
10
8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
A
Microchip Technology Company
Read (25/33 MHz)
The Read instruction, 03H, supports up to 25 MHz (for SST25VF080B-50-xx-xxxx) or 33 MHz (for
SST25VF080B-80-xx-xxxx) Read. The device outputs the data starting from the specified address
location. The data output stream is continuous through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will automatically increment until the highest memory
address is reached. Once the highest memory address is reached, the address pointer will automati-
cally increment to the beginning (wrap-around) of the address space. Once the data from address
location 1FFFFFH has been read, the next output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-
A0]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read
sequence.
Figure 5: Read Sequence
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of
data to be programmed. Data Byte 0 will be programmed into the initial address [A
23
-A
1
] with A
0
=0, Data Byte 1 will be
programmed into the
initial address [A
23
-A
1
] with A
0
=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A
0
=0, and Device ID is read with A
0
=1. All other address bits are 00H. The Manufac-
turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
1296 ReadSeq 0.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
03
HIGH IMPEDANCE
15 16
23
24
31
32
39
40
7047 48 55 56 63 64
N+2 N+3 N+4N N+1
D
OUT
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
©2011 Silicon Storage Technology, Inc. DS25045A 09/11
11
8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
A
Microchip Technology Company
High-Speed-Read (66/80 MHz)
The High-Speed-Read instruction supporting up to 66 MHz (for SST25VF080B-50-xx-xxxx) or 80 MHz
(for SST25VF040B-80-xx-xxxx) Read is initiated by executing an 8-bit command, 0BH, followed by
address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-
Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-
fied address location. The data output stream is continuous through all addresses until terminated by a
low to high transition on CE#. The internal address pointer will automatically increment until the high-
est memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. Once the data from
address location FFFFFH has been read, the next output will be from address location 00000H.
Figure 6: High-Speed-Read Sequence
1296 HSRdSeq.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 39 40
47 48 55 56 63 64
N+2 N+3 N+4
N
N+1
X
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
80
71 72
D
OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
IL
or V
IH
)
©2011 Silicon Storage Technology, Inc. DS25045A 09/11
12
8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
A
Microchip Technology Company
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A
23
-A
0
]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait T
BP
for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
Figure 7: Byte-Program Sequence
1296 ByteProg.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD. D
IN
02
HIGH IMPEDANCE
15 16
23
24
31
32
39
MODE 0
MODE 3
MSBMSB
MSB
LSB

SST25VF080B-80-4I-S2AE

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 8M (1Mx8) 80MHz 2.7-3.6V Industrial
Lifecycle:
New from this manufacturer.
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