FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
13 Rev A 4/7/15
843003 DATA SHEET
Crystal Input Interface
The 843003 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 3
below were determined using a 31.25MHz or 26.041666MHz
18pF parallel resonant crystal and were chosen to minimize the
ppm error.
Figure 3. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50 applications, R1
and R2 can be 100. This can also be accomplished by removing
R1 and making R2 50.
Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
33pF
C2
27pF
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50
Ω
0.1µf
R1
R2
V
CC
V
CC
Rev A 4/7/15 14 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843003 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
15 Rev A 4/7/15
843003 DATA SHEET
Layout Guideline
Figure 6A shows a schematic example of the 843003. An example
of LVEPCL termination is shown in this schematic. Additional
LVPECL termination approaches are shown in the LVPECL
Termination Application Note. In this example, an 18 pF parallel
resonant 31.25MHz crystal is used. The C1= 27pF and
C2 = 33pF are recommended for frequency accuracy. The C1 and
C2 may be slightly adjusted for optimizing frequency accuracy.
Figure 6A. 843003 Schematic Example
PC Board Layout Example
Figure 5B shows an example of 843003 P.C. board layout. The
crystal X1 footprint shown in this example allows installation of
either surface mount HC49S or through-hole HC49 package. The
footprints of other components in this example are listed in the
Table 7. There should be at least one decoupling capacitor per
power pin. The decoupling capacitors should be located as close
as possible to the power pins. The layout assumes that the board
has clean analog power ground plane.
Figure 6B. 843003 PC Board Layout Example Table 7. Footprint Table
NOTE: Table 7, lists component sizes shown in this layout
example.
R7
133
C2
33pF
Set Logic
Input to
'0'
VCCA
VCCO=3.3V
R6
82.5
RD2
1K
VCC
RU2
Not Install
VDD
C8
0.1u
C3
10uF
R9
133
Zo = 50 Ohm
VDD
+
-
RU1
1K
3.3V
R2
10
VCC
X1
31.25MHz
R4
82.5
U1
ICS843003
1
2
3
4
5
6
7
8
9
10
11
1213
14
15
16
17
18
19
20
21
22
23
24
DIV_SELB0
VCO_SEL
MR
VCCO_A
QA0
nQA0
OEB
OEA
FB_DIV
VCCA
VCC
DIV_SELA0DIV_SELA1
VEE
XTAL_OUT
XTAL_IN
TEST_CLK
XTAL_SEL
nQB1
QB1
nQB0
QB0
VCCO_B
DIV_SELB1
+
-
To Logic
Input
pins
C7
0.1u
Set Logic
Input to
'1'
VCCO
R5
133
Zo = 50 Ohm
R10
82.5
C1
27pF
VCC=3.3V
R8
82.5
R3
133
Zo = 50 Ohm
VCCO
RD1
Not Install
C4
0.01u
Logic Control Input Examples
Zo = 50 Ohm
C6
0.1u
To Logic
Input
pins
3.3V
Reference Size
C1, C2 0402
C3 0805
C4, C5, C6, C7, C8 0603
R2 0603

843003AGLFT

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 3 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
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