FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
16 Rev A 4/7/15
843003 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843003.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843003 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 158mA = 547.5mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 3 * 30mW = 90mW
Total Power_
MAX
(3.3V, with all outputs switching) = 547.5mW + 90mW = 637.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate
air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 8below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.638W * 65°C/W = 111.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 8. Thermal Resitance
JA
for 24 Lead TSSOP, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65 62
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
17 Rev A 4/7/15
843003 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage
of V
CCO
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.9V
(V
CCO_MAX
– V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
COO_MAX
– 1.7V
(V
CCO_MAX
– V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) = [(2V – (V
CCO_MAX
– V
OH_MAX
))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) = [(2V – (V
CCO_MAX
– V
OL_MAX
))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CCO
V
CCO
- 2V
Q1
RL
50Ω
Rev A 4/7/15 18 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843003 DATA SHEET
Reliability Information
Table 9.
JA
vs. Air Flow Table for a 24 Lead TSSOP
Transistor Count
The transistor count for 843003 is: 3767
Package Outline and Package Dimension
Package Outline - G Suffix for 24 Lead TSSOP Table 10. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65 62
All Dimensions in Millimeters
Symbol Minimum Maximum
N 24
A 1.20
A1 0.5 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 7.70 7.90
E 6.40 Basic
E1 4.30 4.50
e 0.65 Basic
L 0.45 0.75
aaa 0.10

843003AGLFT

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 3 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
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