74AHC_AHCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 July 2013 10 of 19
NXP Semiconductors 74AHC259-Q100; 74AHCT259-Q100
8-bit addressable latch
[1] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
=5.0V).
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] t
pd
is the same as t
PHL
only.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
11. Waveforms
t
su
set-up time D, An to LE; see Figure 9
and Figure 10
4.0 - - 4.0 - 4.0 - ns
t
h
hold time D, An to LE; see Figure 9
and Figure 10
1.0 - - 1.0 - 1.0 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
=GNDtoV
CC
[4]
-17- - - - -pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
Measurement points are given in Table 9.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 5. Data input to output propagation delays
001aah123
D input
Qn output
t
PHL
t
PLH
GND
V
CC
V
M
V
M
V
OH
V
OL
