74AHC_AHCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 July 2013 9 of 19
NXP Semiconductors 74AHC259-Q100; 74AHCT259-Q100
8-bit addressable latch
t
pd
propagation
delay
MR to Qn; see Figure 8
[3]
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF - 5.4 10.5 1.0 12.5 1.0 13.5 ns
C
L
= 50 pF - 7.0 13.5 1.0 15.5 1.0 17.0 ns
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF - 3.9 7.0 1.0 8.5 1.0 9.5 ns
C
L
= 50 pF - 5.1 9.0 1.0 10.5 1.0 11.5 ns
t
W
pulse width LE HIGH or LOW;
see Figure 7
V
CC
= 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
V
CC
= 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
MR
LOW; see Figure 8
V
CC
= 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
V
CC
= 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
t
su
set-up time D, An to LE; see Figure 9
and Figure 10
V
CC
= 3.0 V to 3.6 V 4.0 - - 4.0 - 4.0 - ns
V
CC
= 4.5 V to 5.5 V 4.0 - - 4.0 - 4.0 - ns
t
h
hold time D, An to LE; see Figure 9
and Figure 10
V
CC
= 3.0 V to 3.6 V 1.0 - - 1.0 - 1.0 - ns
V
CC
= 4.5 V to 5.5 V 1.0 - - 1.0 - 1.0 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
=GNDtoV
CC
[4]
-13- - - - -pF
74AHCT259-Q100; V
CC
= 4.5 V to 5.5 V
t
pd
propagation
delay
D to Qn; see Figure 5
[2]
C
L
= 15 pF - 4.1 7.5 1.0 9.0 1.0 10.0 ns
C
L
= 50 pF - 5.4 9.5 1.0 11.0 1.0 12.0 ns
An to Qn; see Figure 6
[2]
C
L
= 15 pF - 5.5 9.5 1.0 11.5 1.0 12.5 ns
C
L
= 50 pF - 6.6 12.0 1.0 14.0 1.0 15.5 ns
LE
to Qn; see Figure 7
[2]
C
L
= 15 pF - 4.3 8.0 1.0 9.5 1.0 10.4 ns
C
L
= 50 pF - 5.5 10.0 1.0 12.0 1.0 13.0 ns
MR
to Qn; see Figure 8
[3]
C
L
= 15 pF - 3.9 7.0 1.0 8.5 1.0 9.5 ns
C
L
= 50 pF - 5.1 9.0 1.0 10.5 1.0 11.5 ns
t
W
pulse width LE HIGH or LOW;
see Figure 7
5.0 - - 5.0 - 5.0 - ns
MR
LOW; see Figure 8 5.0 - - 5.0 - 5.0 - ns
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max