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74AHC259PW-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
74AHC_AHCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 July 2013 13 of 19
NXP Semiconductors 74AHC259-Q100; 74AHCT259-Q100
8-bit addressable latch
Test data is given in Table 10.
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= load capacitance including jig and probe capacitance.
Fig 11. Load circuitry for measuring switching times
001aah768
t
W
t
W
t
r
t
r
t
f
V
M
V
I
negative
pulse
GND
V
I
positive
pulse
GND
10 %
90 %
90 %
10 %
V
M
V
M
V
M
t
f
V
CC
DUT
R
T
V
I
V
O
C
L
G
Table 10. Test data
Type Input Load Test
V
I
t
r
, t
f
C
L
74AHC259-Q100 V
CC
3.0ns 15pF, 50pF t
PLH
, t
PHL
74AHCT259-Q100 3.0 V 3.0ns 15pF, 50pF t
PLH
, t
PHL
74AHC_AHCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 July 2013 14 of 19
NXP Semiconductors 74AHC259-Q100; 74AHCT259-Q100
8-bit addressable latch
12. Package outline
Fig 12. Package outline SOT109-1 (SO16)
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(1) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1
99-12-27
03-02-19
076E07 MS-012
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74AHC_AHCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 July 2013 15 of 19
NXP Semiconductors 74AHC259-Q100; 74AHCT259-Q100
8-bit addressable latch
Fig 13. Package outline SOT403-1 (TSSOP16)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153
99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
18
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
A
max.
1.1
pin 1 index
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

74AHC259PW-Q100J

Mfr. #:
Buy 74AHC259PW-Q100J
Manufacturer:
NXP Semiconductors
Description:
Latches 8-bit addressable latch
Lifecycle:
New from this manufacturer.
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